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ISL88012IH529Z Datasheet(PDF) 5 Page - Intersil Corporation |
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ISL88012IH529Z Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 11 page  5 FN8093.0 February 13, 2006 Pin Description RST The push-pull RST output is set to VDD (HIGH) whenever 1) the device is first powered up, 2) either VDD or the voltage on VMON falls below their respective minimum voltage sense levels, 3) MR is asserted or 4) the watchdog timeout expires. RST/MR This pin functions as both a reset output and a manual reset input. The RST output functions identically to the complementary RST output but is an open drain output that is pulled to GND (LOW) when reset is asserted. The MR input is an active-low debounced input to which a user can connect a push-button to add manual reset capability or drive with active low signal from a controller. VDD The VDD pin is the power supply terminal. It is monitored by the ISL88011, ISL88012 and ISL88013. For these devices, the voltage at this pin is compared against an internal factory-programmed voltage trip point, VTHVDD. A reset is first asserted when the device is initially powered up to ensure that the power supply has stabilized. Thereafter, reset is again asserted whenever VDD falls below VTHVDD. The device is designed with hysteresis to help prevent chattering due to noise. VMON The VMON pin on the ISL88012, ISL88014 and ISL88015 is a monitored input voltage that is user-adjustable. The voltage at this pin is compared against an internal 600mV reference voltage (VTHVMON) and a reset is asserted whenever the monitored voltage falls below this trip point. WDI The Watchdog Input takes an input from a microprocessor and ensures that it periodically toggles the WDI pin, otherwise the internal watchdog timer runs out and reset is asserted. The internal Watchdog Timer is cleared whenever the WDI input pin sees a rising or falling edge or the device is manually reset. CPOR The CPOR input pin lets users increase the Power On Reset timeout delay (tPOR) by connecting a capacitor between CPOR and ground. (See Figure 3) VTHVMON HYST Hysteresis Voltage (Note 5) 3 mV RESET VOL Reset Output Voltage Low VDD ≥ 3.3V, Sinking 0.5mA 0.05 0.40 V VDD < 3.3V, Sinking 0.5mA 0.05 0.40 V VOH Reset Output Voltage High VDD ≥ 3.3V, Sourcing 0.4mA VDD-0.6 VDD-0.4 V VDD < 3.3V, Sourcing 0.4mA VDD-0.6 VDD-0.4 V tRPD VTH to Reset Asserted Delay 6 µs tPOR POR Timeout Delay ISL88012, ISL88013, ISL88015 140 200 260 ms ISL88011, ISL88014 with CPOR = OPEN 200 250 ms CLOAD Load Capacitance on Reset Pins 5 pF MANUAL RESET VMR MR Input Voltage 0 100 mV tMR MR Minimum Pulse Width 1 µs WATCHDOG TIMER (Note 6) Start tWDT Startup Watchdog Timeout Period 32 51 64 sec tWDT Normal Watchdog Timeout Period 1.0 1.6 2.0 sec tWDPS WDI Minimum Pulse Width 100 ns VIL Watchdog Input Voltage Low 0.3 x VDD V VIH Watchdog Input Voltage High 0.85 x VDD V IWDT Watchdog Input Current 100 nA NOTES: 5. Applies to ISL88012, ISL88014, and ISL88015. 6. Applies to ISL88013 and ISL88015. Electrical Specifications Over the recommended operating conditions unless otherwise specified, RPU = 10kΩ. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ISL88011, ISL88012, ISL88013, ISL88014, ISL88015 |
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