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PGA116 Datasheet(PDF) 9 Page - Texas Instruments |
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PGA116 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 38 page  www.ti.com AV DD CH5 CH4 CH3 CH2 CH1 V /CH0 CAL V REF V OUT CH7 CH6 DV DD CS DOUT DIN SCLK GND ENABLE CH9 CH8 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PGA116 PGA117 PGA112 ,, PGA113 PGA116, PGA117 SBOS424 – MARCH 2008 TSSOP-20 PW PACKAGE (TOP VIEW) PGA116, PGA117 TERMINAL FUNCTIONS TSSOP PACKAGE PIN # NAME DESCRIPTION 1 AVDD Analog supply voltage (+2.2V to +5.5V) 2 CH5 Input MUX channel 5 3 CH4 Input MUX channel 4 4 CH3 Input MUX channel 3 5 CH2 Input MUX channel 2 6 CH1 Input MUX channel 1 Input MUX channel 0 and VCAL input. For system calibration purposes, connect this pin to a low-impedance external reference voltage to use internal calibration channels. The four internal 7 VCAL/CH0 calibration channels are connected to GND, 0.9VCAL, 0.1VCAL, and VREF, respectively. VCAL is loaded with 100k Ω (typical) when internal calibration channels CAL2 or CAL3 are selected. Otherwise, VCAL/CH0 appears as high impedance. Reference input pin. Connect external reference for VOUT offset shift or to midsupply for midsupply 8 VREF referenced systems. VREF must be connected to a low-impedance reference capable of sourcing and sinking at least 2mA or to GND. 9 VOUT Analog voltage output. When AVDD < DVDD, VOUT is clamped to AVDD + 300mV. 10 CH7 Input MUX channel 7 11 CH8 Input MUX channel 8 12 CH9 Input MUX channel 9 13 ENABLE Hardware enable pin. Logic low puts the part into Shutdown mode (IQ < 1µA). 14 GND Ground pin 15 SCLK Clock input for SPI serial interface Data input for SPI serial interface. DIN contains a weak, 10 µA internal pull-down current source to 16 DIN allow for ease of daisy-chain configurations. Data output for SPI serial interface. DOUT goes to high-Z state when CS goes high for standard SPI 17 DOUT interface. 18 CS Chip select line for SPI serial interface Digital and op amp output stage supply voltage (+2.2V to +5.5V). Useful in multi-supply systems to prevent overvoltage/lockup condition on an ADC input (for example, a microcontroller with an ADC 19 DVDD running on +3V and the PGA powered from +5V). Digital I/O levels to be relative to DVDD. DVDD should be bypassed with a 0.1 µF ceramic capacitor, and DV DD must supply the current for the digital portion of the PGA as well as the load current for the op amp output stage. 20 CH6 Input MUX channel 6 Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): PGA112 PGA113 |
Similar Part No. - PGA116 |
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Similar Description - PGA116 |
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