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R

TH [

22.4 kW

V

AST

mVp*p * 1

) 560 W

(1)

V

AST

[

22.4 mVp*p

R

TH

kW * 0.56

) 1 mVp*p

(2)

BANDGAP VOLTAGE AND BIAS GENERATION

PACKAGE

1

2

3

4

VCC

DIN+

DIN−

VCC

RGT PACKAGE

(TOP VIEW)

12

11

10

9

16

VCC

DOUT+

DOUT−

OUTPOL

15

14

13

5

6

7

8

P0019-01

EP

ONET4251PA

SLLS663A – SEPTEMBER 2005 – REVISED NOVEMBER 2005

The ONET4251PA limiting amplifier is supplied by a single 3.3-V

±10% supply voltage connected to the VCC

pins. This voltage is referred to ground (GND).

An on-chip bandgap voltage circuitry generates a supply voltage independent reference from which all other

internally required voltages and bias currents are derived.

For the ONET4251PA a small footprint 3-mm

× 3-mm 16-pin QFN package, with a lead pitch of 0,5 mm is used.

The pin out is shown in Figure 2.

Figure 2. Pinout of ONET4251PA in a 3 mm x 3 mm 16-Pin QFN Package (Top View)

TERMINAL FUNCTIONS

TERMINAL

TYPE

DESCRIPTION

NO.

NAME

1, 4, 12

VCC

supply

3.3-V

±10% supply voltage

2

DIN+

analog-in

Non-inverted data input. On-chip 50-

Ω terminated to VCC.

3

DIN-

analog-in

Inverted data input. On-chip 50-

Ω terminated to VCC.

5

TH

analog-in

LOS threshold adjustment with resistor to GND.

6

DISABLE

CMOS-in

Disables CML output stage when set to high level.

7

LOS

CMOS-out

High level indicates that the input signal amplitude is below the programmed threshold level.

8, 16, EP

GND

supply

Circuit ground. Exposed die pad (EP) must be grounded.

Output data signal polarity select (internally pulled high). Setting to a high level or leaving the pin

9

OUTPOL

CMOS-in

open selects normal polarity. Low level selects inverted polarity.

10

DOUT-

CML-out

Inverted data output. On-chip 50-

Ω back-terminated to VCC.

11

DOUT+

CML-out

Non-inverted data output. On-chip 50-

Ω back-terminated to VCC

3