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NCV8518APWG Datasheet(PDF) 7 Page - ON Semiconductor |
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NCV8518APWG Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 13 page NCV8518A http://onsemi.com 7 TIMING DIAGRAMS VIN, ENABLE RESET Wake Up WDI VOUT POR RESET Delay Time RESET High to Wake Up Delay Time Wake Up Period POR RESET Wake Up WDI VIN, ENABLE RESET Threshold POR VOUT Decreasing Power Down Wake Up Period Figure 2. Power Up, Sleep Mode and Normal Operation VIN, ENABLE RESET Wake Up WDI VOUT Wake Up Duty Cycle = 50% Power Up Microprocessor Sleep Mode Normal Operation with Varying Watchdog Signal RESET High to Wake Up Delay Time POR Wake Up Duty Cycle will be 50% when the WDI pulse occurs at the low state of the Wake Up Signal. Figure 3. Error Condition: Watchdog Remains Low and a RESET is Issued VOUT Min WDI falling edge delay after Wake Up rising edge Wake Up Response to Reset Wake Up Response to WDI Figure 4. Power Down, Restart Sequence, and Wake Up Response to WDI |
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