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M27V801-150F1TR Datasheet(PDF) 2 Page - STMicroelectronics |
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M27V801-150F1TR Datasheet(HTML) 2 Page - STMicroelectronics |
2 / 16 page M27V801 2/16 Figure 2B. PLCC Pin Connections AI01904 A8 A10 17 A1 A0 Q0 A7 A4 A3 A2 A6 A5 9 A9 1 A11 A13 Q7 32 M27V801 A14 GVPP E 25 Figure 2A. DIP Pin Connections A1 A0 Q0 A7 A4 A3 A2 A6 A5 A13 A10 A8 A9 Q7 A14 A11 GVPP E Q5 Q1 Q2 Q3 VSS Q4 Q6 A17 A18 A16 A12 A19 VCC A15 AI01903 M27V801 8 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Figure 2C. TSOP Pin Connections A1 A0 Q0 A7 A4 A3 A2 A6 A5 A13 A10 A8 A9 Q7 A14 A11 GVPP E Q5 Q1 Q2 Q3 Q4 Q6 A17 A18 A16 A12 A19 VCC A15 AI01905 M27V801 (Normal) 8 1 9 16 17 24 25 32 VSS For applications where the content is programmed only one time and erasure is not required, the M27V801 is offered in PDIP32, PLCC32 and TSOP32 (8 x 20 mm) packages. DEVICE OPERATION The operating modes of the M27V801 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for GVPP and 12V on A9 for Elec- tronic Signature and Margin Mode Set or Reset . Read Mode The M27V801 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, indepen- dent of device selection. Assuming that the ad- dresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been sta- ble for at least tAVQV-tGLQV. |
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