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ST7L05 Datasheet(PDF) 23 Page - STMicroelectronics |
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ST7L05 Datasheet(HTML) 23 Page - STMicroelectronics |
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23 / 104 page  ST7L05, ST7L09 23/104 7 SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. Main features ■ Clock Management – 1 MHz internal RC oscillator (enabled by op- tion byte) – External Clock Input (enabled by option byte) – PLL for multiplying the frequency by 8 ■ Reset Sequence Manager (RSM) 7.1 INTERNAL RC OSCILLATOR ADJUSTMENT The ST7 contains an internal RC oscillator with an accuracy of 1% for a given device, temperature and voltage. It must be calibrated to obtain the fre- quency required in the application. This is done by software writing a calibration value in the RCCR (RC Control Register). Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), that is, each time the device is reset, the calibration value must be loaded in the RCCR. The predefined calibration value is stored in EEPROM for 5V VDD supply volt- age at 25°C, as shown in the following table. Notes: – See “ELECTRICAL CHARACTERISTICS” on page 73. for more information on the frequency and accuracy of the RC oscillator. – To improve clock stability and frequency accura- cy, it is recommended to place a decoupling ca- pacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device. – This byte is systematically programmed by ST, including on FASTROM devices. Consequently, customers intending to use FASTROM service must not use this byte. – RCCR0 and RCCR1 calibration values are erased if the read-out protection bit is reset after it has been set. See “Read-out Protection” on page 14. Caution: If the voltage or temperature conditions change in the application, the frequency may re- quire recalibration. Refer to application note AN1324 for information on how to calibrate the RC frequency using an ex- ternal reference signal. 7.2 PHASE LOCKED LOOP The PLL is used to multiply a 1 MHz frequency from the RC oscillator or the external clock by 8 to obtain fOSC of 8 MHz. The PLL is enabled (by 1 op- tion bit) and the multiplication factor is 8. The x8 PLL is intended for operation with VDD in the 3.6 to 5.5V range Refer to Section 15.2 for the option byte descrip- tion. If the PLL is disabled and the RC oscillator is ena- bled, then fOSC = 1 MHz. If both the RC oscillator and the PLL are disabled, fOSC is driven by the external clock. Figure 11. PLL Output Frequency Timing Diagram When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs the clock after a delay of tSTARTUP. When the PLL output signal reaches the operating frequency, the LOCKED bit in the SICSCR register is set. Full PLL accuracy (ACCPLL) is reached after a stabilization time of tSTAB (see Figure 11 and section 13.3.2 Internal RC Oscillator and PLL). RCCR Conditions ST7FL09 Address ST7FL05 Address RCCR0 VDD = 5V TA = 25°C fRC = 1 MHz 1000h and FFDEh FFDEh RCCR1 VDD = 3.3V TA = 25°C fRC = 700 kHz 1001h and FFDFh FFDFh 8 x freq. LOCKED bit set tSTAB tLOCK input tSTARTUP t 1 |
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