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SN75LVDS84ADGGR Datasheet(PDF) 4 Page - Texas Instruments |
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SN75LVDS84ADGGR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 16 page SN75LVDS84A, SN65LVDS84AQ FLATLINK TRANSMITTER SLLS354E – MAY 1999 – REVISED JANUARY 2001 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements MIN NOM MAX UNIT tc Input clock period 13.3 tc 32.4 ns tw Pulse duration, high-level input clock 0.4 tc 0.6 tc ns tt Transition time, input signal 5 ns tsu Setup time, data, D0 – D20 valid before CLKIN ↓ (see Figure 2) 3 ns th Hold time, data, D0 – D20 valid after CLKIN ↓ (see Figure 2) 1.5 ns electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIT Input threshold voltage 1.4 V |VOD| Differential steady-state output voltage magnitude RL = 100 Ω, See Figure 3 247 454 mV ∆|VOD| Change in the steady-state differential output voltage magnitude between opposite binary states 50 mV VOC(SS) Steady-state common-mode output voltage RL = 100 Ω, See Figure 3 1.125 1.375 V VOC(PP) Peak-to-peak common-mode output voltage 80 150 mV IIH High level input current VIH =VCC SN75LVDS84A 20 µA IIH High-level input current VIH = VCC SN65LVDS84AQ 25 µA IIL Low-level input current VIL = 0 ±10 µA IOS Short circuit output current VO(Yn) = 0 –6 ±24 mA IOS Short-circuit output current VOD = 0 –6 ±12 mA IOZ High-impedance output current VO = 0 to VCC ±10 µA Disabled, SN75LVDS84A 15 150 µA , All inputs at GND SN65LVDS84AQ 15 170 µA Enabled, RL = 100 Ω (4 places) f = 65 MHz 27 35 ICC(AVG) Quiescent supply current (average) L () Gray-scale pattern (see Figure 4) f = 75 MHz 30 38 mA Enabled, RL = 100 Ω, (4 places) f = 65 MHz 28 36 mA L ,( ) Worst-case pattern (see Figure 5) f = 75 MHz 31 39 CI Input capacitance 2 pF † All typical values are at VCC = 3.3 V, TA = 25°C. |
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