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SN75LVDS84A Datasheet(PDF) 5 Page - Texas Instruments |
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SN75LVDS84A Datasheet(HTML) 5 Page - Texas Instruments |
5 / 16 page SN75LVDS84A, SN65LVDS84AQ FLATLINK TRANSMITTER SLLS354E – MAY 1999 – REVISED JANUARY 2001 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT td0 Delay time, CLKOUT ↑ to serial bit position 0 – 0.2 0.2 td1 Delay time, CLKOUT ↑ to serial bit position 1 1 7 tc * 0.2 1 7 tc ) 0.2 td2 Delay time, CLKOUT ↑ to serial bit position 2 2 7 tc * 0.2 2 7 tc ) 0.2 td3 Delay time, CLKOUT ↑ to serial bit position 3 tc = 15.38 ns (± 0.2%), |Input clock jitter| < 50 ps‡, See Figure 6 3 7 tc * 0.2 3 7 tc ) 0.2 ns td4 Delay time, CLKOUT ↑ to serial bit position 4 4 7 tc * 0.2 4 7 tc ) 0.2 td5 Delay time, CLKOUT ↑ to serial bit position 5 5 7 tc * 0.2 5 7 tc ) 0.2 td6 Delay time, CLKOUT ↑ to serial bit position 6 6 7 tc * 0.2 6 7 tc ) 0.2 tsk(o) Output skew, tn * n 7 tc – 0.2 0.2 ns td7 Delay time CLKIN ↓ to CLKOUT↑ tc = 15.38 ns (± 0.2%), |Input clock jitter| < 50 ps‡, See Figure 6 2.7 ns td7 Delay time, CLKIN ↓ to CLKOUT↑ tc = 13.33 ns ~ 32.25 ns (± 0.2%), |Input clock jitter| < 50 ps‡, See Figure 6 1 4.5 ns ∆t () C cle time o tp t clock jitter§ tc = 15.38 + 0.308 sin (2π500E3t) ± 0.05 ns, See Figure 7 ±62 ps ∆tc(o) Cycle time, output clock jitter§ tc = 15.38 + 0.308 sin (2π3E6t) ± 0.05 ns, See Figure 7 ±121 ps tw Pulse duration, high-level output clock 4 7 tc ns tt Transition time, differential output voltage (tr or tf) See Figure 3 700 1500 ps ten Enable time, SHTDN ↑ to phase lock (Yn valid) See Figure 8 1 ms tdis Disable time, SHTDN ↓ to off state (CLKOUT low) See Figure 9 6.5 ns † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ |Input clock jitter| is the magnitude of the change in the input clock period. § Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15 000 cycles. |
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