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TMS320C6211B Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320C6211B Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 87 page  TMS320C6211, TMS320C6211B FIXEDPOINT DIGITAL SIGNAL PROCESSORS SPRS073L − AUGUST 1998 − REVISED JUNE 2005 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 D Excellent Price/Performance Digital Signal Processors (DSPs): TMS320C62x (TMS320C6211 and TMS320C6211B) − Eight 32-Bit Instructions/Cycle − C6211, C6211B, C6711, and C6711B are Pin-Compatible − 150-, 167-MHz Clock Rates − 6.7-, 6-ns Instruction Cycle Time − 1 200, 1333 MIPS − Extended Temperature Device (C6211B) D VelociTI Advanced Very Long Instruction Word (VLIW) C62x DSP Core (C6211/11B) − Eight Highly Independent Functional Units: − Six ALUs (32-/40-Bit) − Two 16-Bit Multipliers (32-Bit Results) − Load-Store Architecture With 32 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional D Instruction Set Features − Byte-Addressable (8-, 16-, 32-Bit Data) − 8-Bit Overflow Protection − Saturation − Bit-Field Extract, Set, Clear − Bit-Counting − Normalization D L1/L2 Memory Architecture − 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped) − 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative) − 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation) D Device Configuration − Boot Mode: HPI, 8-, 16-, and 32-Bit ROM Boot − Endianness: Little Endian, Big Endian D 32-Bit External Memory Interface (EMIF) − Glueless Interface to Asynchronous Memories: SRAM and EPROM − Glueless Interface to Synchronous Memories: SDRAM and SBSRAM − 512M-Byte Total Addressable External Memory Space D Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels) D 16-Bit Host-Port Interface (HPI) − Access to Entire Memory Map D Two Multichannel Buffered Serial Ports (McBSPs) − Direct Interface to T1/E1, MVIP, SCSA Framers − ST-Bus-Switching Compatible − Up to 256 Channels Each − AC97-Compatible − Serial-Peripheral-Interface (SPI) Compatible (Motorola ) D Two 32-Bit General-Purpose Timers D Flexible Phase-Locked-Loop (PLL) Clock Generator D IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible D 256-Pin Ball Grid Array (BGA) Package (GFN and ZFN Suffixes) D 0.18-µm/5-Level Metal Process − CMOS Technology D 3.3-V I/Os, 1.8-V Internal Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. All trademarks are the property of their respective owners. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. |
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