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NAND08GW3C4BN1F Datasheet(PDF) 9 Page - Numonyx B.V |
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NAND08GW3C4BN1F Datasheet(HTML) 9 Page - Numonyx B.V |
9 / 60 page NAND08GW3C2B, NAND16GW3C4B 1 Description 9/60 Figure 2. Logic diagram 1. E2 and RB2 are only present in the NAND16GW3C4A. Table 2. Signal names Signal Function Direction I/O0 - I/O7 Data input/outputs(1) 1. On the LGA52 package, each 8-Gbit die is accessed and controlled via two sets of I/Os and control signals. Input/output CL Command Latch Enable Input AL Address Latch Enable Input E1, E2 Chip Enable(2) Input R Read Enable Input W Write Enable Input WP Write Protect Input RB1, RB2 Ready/Busy (open drain output)(2) 2. E2 and RB2 are only present in the NAND16GW3C4B. Output VDD Power supply Power supply VSS Ground Ground NC No connection DU Do not use AI13632b I/O0 - I/O7 x8 VDD NAND Flash W VSS WP AL CL E1 R RB1 E2 RB2 |
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