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M25P10-A Datasheet(PDF) 12 Page - STMicroelectronics

Part No. M25P10-A
Description  1 Mbit, Low Voltage, Serial Flash Memory With 25 MHz SPI Bus Interface
Download  41 Pages
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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M25P10-A Datasheet(HTML) 12 Page - STMicroelectronics

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INSTRUCTIONS
All instructions, addresses and data are shifted in
and out of the device, most significant bit first.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S) is
driven Low. Then, the one-byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 4.
Every instruction sequence starts with a one-byte
instruction code. Depending on the instruction,
this might be followed by address bytes, or by data
bytes, or by both or none. Chip Select (S) must be
driven High after the last bit of the instruction se-
quence has been shifted in.
In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast_Read), Read
Identification (RDID), Read Status Register (RD-
SR) or Release from Deep Power-down, and
Read Electronic Signature (RES) instruction, the
shifted-in instruction sequence is followed by a
data-out sequence. Chip Select (S) can be driven
High after any bit of the data-out sequence is be-
ing shifted out.
In the case of a Page Program (PP), Sector Erase
(SE), Bulk Erase (BE), Write Status Register
(WRSR), Write Enable (WREN), Write Disable
(WRDI) or Deep Power-down (DP) instruction,
Chip Select (S) must be driven High exactly at a
byte boundary, otherwise the instruction is reject-
ed, and is not executed. That is, Chip Select (S)
must driven High when the number of clock pulses
after Chip Select (S) being driven Low is an exact
multiple of eight.
All attempts to access the memory array during a
Write Status Register cycle, Program cycle or
Erase cycle are ignored, and the internal Write
Status Register cycle, Program cycle or Erase cy-
cle continues unaffected.
Table 4. Instruction Set
Note: 1. The Read Identification (RDID) instruction is available only in products with Process Technology code X (see Application Note
AN1995).
Instruction
Description
One-byte Instruction Code
Address
Bytes
Dummy
Bytes
Data
Bytes
WREN
Write Enable
0000 0110
06h
0
0
0
WRDI
Write Disable
0000 0100
04h
0
0
0
RDID(1)
Read Identification
1001 1111
9Fh
0
0
1 to 3
RDSR
Read Status Register
0000 0101
05h
0
0
1 to
WRSR
Write Status Register
0000 0001
01h
0
0
1
READ
Read Data Bytes
0000 0011
03h
3
0
1 to
FAST_READ
Read Data Bytes at Higher Speed
0000 1011
0Bh
3
1
1 to
PP
Page Program
0000 0010
02h
3
0
1 to 256
SE
Sector Erase
1101 1000
D8h
3
0
0
BE
Bulk Erase
1100 0111
C7h
0
0
0
DP
Deep Power-down
1011 1001
B9h
0
0
0
RES
Release from Deep Power-down,
and Read Electronic Signature
1010 1011
ABh
0
3
1 to
Release from Deep Power-down
0
0
0


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