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M58WR016QT Datasheet(PDF) 31 Page - Numonyx B.V

Part # M58WR016QT
Description  16 Mbit and 32 Mbit (x16, Multiple Bank, Burst) 1.8V supply Flash memories
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Manufacturer  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

M58WR016QT Datasheet(HTML) 31 Page - Numonyx B.V

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M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Command interface - factory pro-
31/110
6.4.1
Setup Phase
The Enhanced Factory Program command requires two Bus Write operations to initiate the
command.
The first bus cycle sets up the Enhanced Factory Program command.
The second bus cycle confirms the command.
The Status Register P/E.C. Bit SR7 should be read to check that the P/E.C. is ready. After
the confirm command is issued, read operations output the Status Register data. The read
Status Register command must not be issued as it will be interpreted as data to program.
6.4.2
Program Phase
The Program Phase requires n+1 cycles, where n is the number of Words (refer to Table 8:
Factory Program commands, and Figure 28: Enhanced Factory Program flowchart).
Three successive steps are required to issue and execute the Program Phase of the
command.
1.
Use one Bus Write operation to latch the Start Address and the first Word to be
programmed. The Status Register Bank Write Status bit SR0 should be read to check
that the P/E.C. is ready for the next Word.
2.
Each subsequent Word to be programmed is latched with a new Bus Write operation.
The address can either remain the Start Address, in which case the P/E.C. increments
the address location or the address can be incremented in which case the P/E.C.
jumps to the new address. If any address that is not in the same block as the Start
Address is given with data FFFFh, the Program Phase terminates and the Verify Phase
begins. The Status Register bit SR0 should be read between each Bus Write cycle to
check that the P/E.C. is ready for the next Word.
3.
Finally, after all Words have been programmed, write one Bus Write operation with data
FFFFh to any address outside the block containing the Start Address, to terminate the
programming phase. If the data is not FFFFh, the command is ignored.
The memory is now set to enter the Verify Phase.


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