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M58WR016QT Datasheet(PDF) 35 Page - Numonyx B.V

Part # M58WR016QT
Description  16 Mbit and 32 Mbit (x16, Multiple Bank, Burst) 1.8V supply Flash memories
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Manufacturer  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

M58WR016QT Datasheet(HTML) 35 Page - Numonyx B.V

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M58WR016QT, M58WR016QB, M58WR032QT, M58WR032QB
Status Register
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7
Status Register
The Status Register provides information on the current or previous Program or Erase
operations. Issue a Read Status Register command to read the contents of the Status
Register, refer to Read Status Register Command section for more details. To output the
contents, the Status Register is latched and updated on the falling edge of the Chip Enable
or Output Enable signals and can be read until Chip Enable or Output Enable returns to VIH.
The Status Register can only be read using single asynchronous or single synchronous
reads. Bus Read operations from any address within the bank, always read the Status
Register during Program and Erase operations.
The various bits convey information about the status and any errors of the operation. Bits
SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset
by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the
device but must be reset by issuing a Clear Status Register command or a hardware reset.
If an error bit is set to ‘1’ the Status Register should be reset before issuing another
command. SR7 to SR1 refer to the status of the device while SR0 refers to the status of the
addressed bank.
The bits in the Status Register are summarized in Table 9: Status Register bits. Refer to
Table 9 in conjunction with the following text descriptions.
7.0.1
Program/Erase Controller Status Bit (SR7)
The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is
active or inactive in any bank. When the Program/Erase Controller Status bit is Low (set to
‘0’), the Program/Erase Controller is active; when the bit is High (set to ‘1’), the
Program/Erase Controller is inactive, and the device is ready to process a new command.
The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend
command is issued until the Program/Erase Controller pauses. After the Program/Erase
Controller pauses the bit is High.
During Program, Erase, operations the Program/Erase Controller Status bit can be polled to
find the end of the operation. Other bits in the Status Register should not be tested until the
Program/Erase Controller completes the operation and the bit is High.
After the Program/Erase Controller completes its operation the Erase Status, Program
Status, VPP Status and Block Lock Status bits should be tested for errors.
7.0.2
Erase Suspend Status Bit (SR6)
The Erase Suspend Status bit indicates that an Erase operation has been suspended or is
going to be suspended in the addressed block. When the Erase Suspend Status bit is High
(set to ‘1’), a Program/Erase Suspend command has been issued and the memory is
waiting for a Program/Erase Resume command.
The Erase Suspend Status should only be considered valid when the Program/Erase
Controller Status bit is High (Program/Erase Controller inactive). SR7 is set within the Erase
Suspend Latency time of the Program/Erase Suspend command being issued therefore the
memory may still complete the operation rather than entering the Suspend mode.
When a Program/Erase Resume command is issued the Erase Suspend Status bit returns
Low.


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