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M29W400DT45M1 Datasheet(PDF) 25 Page - Numonyx B.V |
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M29W400DT45M1 Datasheet(HTML) 25 Page - Numonyx B.V |
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25 / 48 page  M29W400DT, M29W400DB Status Register 25/48 5.3 Error bit (DQ5) The Error bit can be used to identify errors detected by the Program/Erase controller. The Error bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’ 5.4 Erase Timer bit (DQ3) The Erase Timer bit can be used to identify the start of Program/Erase controller operation during a Block Erase command. Once the Program/Erase controller starts erasing, the Erase Timer bit is set to ’1’. Before the Program/Erase controller starts the Erase Timer bit is set to ‘0’ and additional blocks to be erased may be written to the command interface. The Erase Timer bit is output on DQ3 when the Status Register is read. 5.5 Alternative Toggle bit (DQ2) The Alternative Toggle bit can be used to monitor the Program/Erase controller during Erase operations. The Alternative Toggle bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error bit to be set the Alternative Toggle bit can be used to identify which block or blocks have caused the error. The Alternative Toggle bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read operations from addresses within blocks that have not erased correctly. The Alternative Toggle bit does not change if the addressed block has erased correctly. Table 7. Status Register bits(1) Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB Program Any address DQ7 Toggle 0 – – 0 Program during Erase Suspend Any address DQ7 Toggle 0 – – 0 Program Error Any address DQ7 Toggle 1 – – 0 Chip Erase Any address 0 Toggle 0 1 Toggle 0 |
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