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M45PE40-VMW6G Datasheet(PDF) 37 Page - Numonyx B.V |
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M45PE40-VMW6G Datasheet(HTML) 37 Page - Numonyx B.V |
37 / 46 page M45PE40 DC and AC parameters 37/46 Table 13. AC characteristics (33 MHz operation) 33 MHz only available for products marked since week 40 of 2005(1) Test conditions specified in Table 8 and Table 9 1. Details of how to find the date of marking are given in Application Note, AN1995. Symbol Alt. Parameter Min. Typ. Max. Unit fC fC Clock Frequency for the following instructions: FAST_READ, PW, PP, PE, SE, DP, RDP, WREN, WRDI, RDSR D.C. 33 MHz fR Clock Frequency for READ instructions D.C. 20 MHz tCH (2) 2. tCH + tCL must be greater than or equal to 1/ fC tCLH Clock High Time 13 ns tCL (2) tCLL Clock Low Time 13 ns Clock Slew Rate(3) (peak to peak) 3. Value guaranteed by characterization, not 100% tested in production. 0.03 V/ns tSLCH tCSS S Active Setup Time (relative to C) 10 ns tCHSL S Not Active Hold Time (relative to C) 10 ns tDVCH tDSU Data In Setup Time 3 ns tCHDX tDH Data In Hold Time 5 ns tCHSH S Active Hold Time (relative to C) 5 ns tSHCH S Not Active Setup Time (relative to C) 5 ns tSHSL tCSH S Deselect Time 200 ns tSHQZ (3) tDIS Output Disable Time 12 ns tCLQV tV Clock Low to Output Valid 12 ns tCLQX tHO Output Hold Time 0 ns tTHSL Top Sector Lock Setup Time 50 ns tSHTL Top Sector Lock Hold Time 100 ns tDP (3) S to Deep Power-down 3 μs tRDP (3) S High to Standby Power mode 30 μs tPW (4) 4. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one sequence including all the Bytes versus several sequences of only a few Bytes. (1 ≤n ≤256) Page Write Cycle Time (256 Bytes) 11 25 ms Page Write Cycle Time (n Bytes) 10.2+ n*0.8/256 tPP (4) Page Program Cycle Time (256 Bytes) 1.2 5ms Page Program Cycle Time (n Bytes) 0.4+ n*0.8/256 tPE Page Erase Cycle Time 10 20 ms tSE Sector Erase Cycle Time 1 5 s |
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