M45PE40 datasheet(8/46 Pages) NUMONYX

Part #	M45PE40

Description	4 Mbit, low voltage, Page-Erasable Serial Flash memory with byte-alterability and a 50 MHz SPI bus interface

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Manufacturer	NUMONYX [Numonyx B.V]

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Signal description

M45PE40

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2

Signal description

2.1

Serial Data Output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of Serial Clock (C).

2.2

Serial Data Input (D)

This input signal is used to transfer data serially into the device. It receives instructions,

addresses, and the data to be programmed. Values are latched on the rising edge of Serial

Clock (C).

2.3

Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on

Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

2.4

Chip Select (S)

When this input signal is High, the device is deselected and Serial Data Output (Q) is at high

impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the

device will be in the Standby Power mode (this is not the Deep Power-down mode). Driving

Chip Select (S) Low selects the device, placing it in the Active Power mode.

After Power-up, a falling edge on Chip Select (S) is required prior to the start of any

instruction.

2.5

Reset (Reset)

The Reset (Reset) input provides a hardware reset for the memory. In this mode, the outputs

are high impedance.

When Reset (Reset) is driven High, the memory is in the normal operating mode. When

Reset (Reset) is driven Low, the memory will enter the Reset mode, provided that no

internal operation is currently in progress. Driving Reset (Reset) Low while an internal

operation is in progress has no effect on that internal operation (a write cycle, program

cycle, or erase cycle).

2.6

Write Protect (W)

This input signal puts the device in the Hardware Protected mode, when Write Protect (W) is

connected to VSS, causing the first 256 pages of memory to become read-only by protecting

them from write, program and erase operations. When Write Protect (W) is connected to

VCC, the first 256 pages of memory behave like the other pages of memory.

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