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S3029A Datasheet(PDF) 3 Page - Applied Micro Circuits Corporation |
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S3029A Datasheet(HTML) 3 Page - Applied Micro Circuits Corporation |
3 / 11 page 3 S3029 SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER February 19, 1999 / Revision B S3029 OVERVIEW The S3029 supports clock recovery for the STS-3/ STM-1 data rate. The LVPECL differential serial data is input to the chip and clock recovery is performed on the incoming data stream. An external reference clock is required to minimize the PLL lock time and provide a stable output clock source in the absence of serial input data. Retimed data and clock are output from the S3029. CHARACTERISTICS Performance The S3029 PLL complies with the minimum jitter tol- erance for clock recovery proposed for SONET/SDH equipment defined by the T1X1.6/91-022 document, when used with differential inputs and outputs as shown in Figure 3. Input Jitter Tolerance Input jitter tolerance is defined as the peak to peak amplitude of sinusoidal jitter applied on the input sig- nal that causes an equivalent 1 dB optical/electrical power penalty. SONET input jitter tolerance require- ments are shown in Figure 3. The measurement condition is the input jitter amplitude which causes an equivalent of 1 dB power penalty. Serial Data Output Set-up and Hold Time The output set-up and hold times are represented by the waveforms shown in Figure 4. Figure 4. Clock Output to Data Transition Delay Output Frequency 155.52 MHz SERDATOP/N Setup Time 2.5 ns SERDATOP/N Hold Time 2.5 ns t su t h SERCLKOP/N SERDATOP/N Figure 3. Input Jitter Tolerance Specification f0 f1 f2 f3 ft 0.15 1.5 15 Sinusodal Input Jitter Amplitude (UI p-p) Frequency OC/STS Level f0 (Hz) f2 (Hz) f3 (kHz) ft (kHz) f1 (Hz) 3 10 30 300 6.5 75 L E S F E R k c o l C e c n e r e f e R ) z H M ( y c n e u q e r F 0z H M 4 4 . 9 1 1z H M 4 8 . 1 5 Table 1. |
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