Soft-Start

The MAX1945R/MAX1945S employs digital soft-start to

reduce supply in-rush current during startup conditions.

When the device exits undervoltage lockout (UVLO),

shutdown mode, or restarts following a thermal-overload

event, the digital soft-start circuitry slowly ramps up the

voltages at REF and FB (see the Typical Operating

Characteristics). An internal oscillator sets the soft-start

time to 3.7ms (typ). Use a of 0.22µF capacitor (min) to

reduce the susceptibility to switching noise.

Undervoltage Lockout (UVLO)

and the soft-start function activates.

Bootstrap (BST)

A capacitor connected between BST and LX and a

Schottky diode connected from IN to BST generate the

gate drive for the internal high-side N-channel MOSFET.

When the low-side N-channel MOSFET is on, LX goes to

PGND. IN charges the bootstrap capacitor through the

Schottky diode. When the low-side N-channel MOSFET

turns off and the high side N-channel MOSFET turns on,

itor from discharging into IN.

Frequency Select (SYNC)

The MAX1945R/MAX1945S operate in PWM mode with

a selectable fixed frequency or synchronized to an

external frequency. The devices switch at a frequency

of 500kHz when SYNC is connected to ground. The

Apply an external frequency of 400kHz to 1.2MHz with

10% to 90% duty cycle at SYNC to synchronize the

switching frequency of MAX1945R/MAX1945S.

Output Voltage Select

The MAX1945R/MAX1945S feature selectable fixed and

adjustable output voltages. With FB connected to the

output, the output voltage is 1.8V when FBSEL is at

FBSEL is floating, connect FB to an external resistor

the 1k

Ω to 10kΩ range. Calculate R1 using the follow-

ing equation:

Shutdown Mode

Drive CTL1 and CTL2 to ground to shut down the

MAX1945R/MAX1945S. In shutdown mode, the internal

MOSFETs stop switching and LX goes to high imped-

ance; REF and COMP go to ground.

Voltage Margining

The MAX1945R/MAX1945S provide selectable voltage

margining. The MAX1945R provides ±4% voltage mar-

gining, and the MAX1945S provides ±9% voltage margin-

ing. CTL1 and CTL2 set the voltage margins (Table 1).

Thermal Protection

Thermal-overload protection limits total power dissipa-

exceeds 165°C, a thermal sensor forces the device into

shutdown, allowing the die to cool. The thermal sensor

turns the device on again after the junction temperature

cools by 20°C, causing a pulsed output during continu-

ous overload conditions.The soft-start sequence begins

after a thermal-shutdown condition.

Design Procedure

Because of the high switching frequency and tight out-

the capacitor as close to VCC as possible.

Inductor Design

Choose an inductor with the following equation:

where LIR is the ratio of the inductor ripple current to

average continuous current at a minimum duty cycle.

Choose LIR between 20% to 40% of the maximum load

current for best performance and stability.

L

VV

V

fV

LIR

I

OUT

IN

OUT

OSC

IN

OUT MAX

=

×

()

××

×

−

()

RR

V

V

OUT

FB

12

1

=









−

1MHz, 1% Accurate, 6A Internal Switch

Step-Down Regulators

12

______________________________________________________________________________________

CTL1

CTL2

MAX1945R

MAX1945S

0V

0V

OFF

OFF

NOMINAL

NOMINAL

0V

-4%

-9%

Voltage Margin

0V

+4%

+9%

Table 1. Setting Voltage Margin