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M5482B7 Datasheet(PDF) 3 Page - STMicroelectronics

Part # M5482B7
Description  LED DISPLAY DRIVER
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

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M5482
Table 2. Static Electrical Characteristics
(Tamb within operating range, VDD = 4.75V to 13.2V, VSS = 0V, unless otherwise specified)
Note: 1. Output matching is calculated as the percent variation from IMAX + IMIN/2.
2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to another.
3. Absolute maximum for each output should be limited to 40mA.
4. The VO voltage should be regulated by the user.
FUNCTIONAL DESCRIPTION
The M5482 uses the M5451 die which is packaged
to operate 2-digit alphanumeric displays with min-
imal interface with the display and the data source.
Serial data transfer from the data source to the dis-
play driver is accomplished with 2 signals, serial
data and clock. Using a format of a leading "1" fol-
lowed by the 35 data bits allows data transfer with-
out an additional load signal.
The 35 data bits are latched after the 36th bit is
complete, thus providing non-multiplexed, direct
drive to the display. Outputs change only if the se-
rial data bits differ from the previous time. Display
brightness is determined by control of the output
current for LED displays. A 1nF capacitor should
be connected to brightness control, Pin 9, to pre-
vent possible oscillations.
A block diagram is shown in Figure 3. The output
current is typically 20 times greater than the cur-
rent into Pin 9, which is set by an external variable
resistor.
There is an internal limiting resistor of 400
Ω nom-
inal value.
Figure 4 shows the input data format. A start bit of
logical "1" precedes the 35 bits of data. At the 36th
clock a LOAD signal is generated synchronously
with the high state of the clock, which loads the 35
bits of the shift registers into the latches.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VDD
Supply Voltage
4.75
13.2
V
IDD
Supply Current
VDD = 13.2V
7mA
VI
Input Voltage Logical "0" Level
± 10µA Input Bias
- 0.3
0.8
V
Logical "1" Level
4.75
≤ VDD ≤ 5.25
2.2
VDD
V
VDD > 5.25
VDD - 2
VDD
V
IB
Brightness Input Current (note 2)
0
0.75
mA
VB
Brightness Input Voltage (pin 9)
Input Current = 750
µA, Tamb = 25°C
34.3
V
VO(off)
Off State Out. Voltage
13.2
V
IO
Out. Sink Current (note 3)
Segment OFF
VO = 3V
10
µA
Segment ON
VO = 1V (note 4)
Brightness In. = 0
µA0
10
µA
Brightness In. = 100
µA2
2,7
4
mA
Brightness In. = 750
µA12
15
25
mA
fclock
Input Clock Frequency
0
0.5
MHz
IO
Output Matching (note 1)
± 20
%


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