M36L0T7050T2 datasheet(14/22 Pages) NUMONYX

Part #	M36L0T7050T2

Description	128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package

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Manufacturer	NUMONYX [Numonyx B.V]

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Functional description

M36L0T7050T2, M36L0T7050B2

14/22

Table 2.

Operating modes(1)

Operation

EF GF WF

LF

RPF WAITF

(2) E1

P

E2P

GP

WP LBP,UBP

DQ0-

DQ7

DQ8-

DQ15

Flash Read

VIL VIL VIH VIL

(3)

VIH

PSRAM must be disabled

Data Out

Flash Write

VIL VIH VIL VIL

(3)

VIH

Data In

Flash Address

Latch

VIL

XVIH

VIL

VIH

Data Out or Hi-Z(4)

Flash Output

Disable

VIL VIH VIH

XVIH

Hi-Z

Any PSRAM mode is allowed

Hi-Z

Flash Standby

VIH

XX

X

VIH

Hi-Z

Flash Reset

X

VIL

Hi-Z

PSRAM Read(5)

Flash Memory must be disabled

VIL

VIH

VIL

VIH

VIL

VIH data out

Hi-Z

VIL

VIH

VIL

VIH VIH

VIL

Hi-Z

data out

VIL

VIH

VIL

VIH

VIL

data out

PSRAM Write(5)

VIL

VIH

VIL

VIH

data in

Hi-Z

VIL

VIH

VIL

VIH

VIL

Hi-Z

data in

VIL

VIH VIH

(6) V

IL

VIL

data in

PSRAM Output

Disabled(5)

Any Flash mode is allowed

VIL

VIH

VIL

VIH

Hi-Z

VIL

VIH

PSRAM Standby

(Deselected)

VIH VIH

XX

X

Hi-Z

PSRAM Power-

Down(7)

XVIL

XX

X

Hi-Z

1.

X = Don't care.

2.

WAIT signal polarity is configured using the Set Configuration Register command. See the M58LT128HTB datasheet for

details.

3.

LF can be tied to VIH if the valid address has been previously latched.

4.

Depends on GF.

5.

Should not be kept in this logic condition for a period longer than 1µs.

6.

GP can be VIL during the Write operation if the following conditions are satisfied:

a. Write pulse is initiated by E1P (E1P Controlled Write timing), or cycle time of the previous operation cycle is satisfied;

b. GP stays VIL during the entire Write cycle.

7.

Power-Down mode can be entered from Standby state and all Data outputs are in High-Z. The Power-Down current and

data retention depend on the selection of Power-Down programming.

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