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M29DW323DT70N1 Datasheet(PDF) 13 Page - Numonyx B.V |
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M29DW323DT70N1 Datasheet(HTML) 13 Page - Numonyx B.V |
13 / 51 page 13/51 M29DW323DT, M29DW323DB BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Out- put Disable, Standby and Automatic Standby. The Dual Bank architecture of the M29DW323 al- lows read/write operations in Bank A, while read operations are being executed in Bank B or vice versa. Write operations are only allowed in one bank at a time. See Tables 3 and 4, Bus Operations, for a summa- ry. Typically glitches of less than 5ns on Chip En- able or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Com- mand Interface. A valid Bus Read operation in- volves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 11., Read Mode AC Waveforms, and Table 15., Read AC Characteristics, for de- tails of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Ad- dress Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Com- mand Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output En- able must remain High, VIH, during the whole Bus Write operation. See Figures 12 and 13, Write AC Waveforms, and Tables 16 and 17, Write AC Characteristics, for details of the timing require- ments. Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH. Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data In- puts/Outputs pins are placed in the high-imped- ance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current level see Table 14., DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations un- til the operation completes. Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or more the memory enters Automatic Standby where the internal Supply Current is re- duced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus opera- tions are intended for use by programming equip- ment and are not usually used in applications. They require VID to be applied to some pins. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 3 and 4, Bus Operations. Block Protect and Chip Unprotect. Groups of blocks can be protected against accidental Pro- gram or Erase. The Protection Groups are shown in APPENDIX A., Tables 23 and 24, Block Ad- dresses. The whole chip can be unprotected to al- low the data inside the blocks to be changed. The VPP/Write Protect pin can be used to protect the two outermost boot blocks. When VPP/Write Protect is at VIL the two outermost boot blocks are protected and remain protected regardless of the Block Protection Status or the Reset/Block Tem- porary Unprotect pin status. Block Protect and Chip Unprotect operations are described in APPENDIX D. |
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