M25PX64-STVME6E datasheet(41/66 Pages) NUMONYX

Part #	M25PX64-STVME6E

Description	64-Mbit, dual I/O, 4-Kbyte subsector erase, serial flash memory with 75 MHz SPI bus interface

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Manufacturer	NUMONYX [Numonyx B.V]

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M25PX64

Instructions

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6.11

Page program (PP)

The page program (PP) instruction allows bytes to be programmed in the memory (changing

bits from ‘1’ to ‘0’). Before it can be accepted, a write enable (WREN) instruction must

previously have been executed. After the write enable (WREN) instruction has been

decoded, the device sets the write enable latch (WEL).

The page program (PP) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code, three address bytes and at least one data byte on serial data input (DQ0).

If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes

beyond the end of the current page are programmed from the start address of the same

page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)

must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 18.

If more than 256 bytes are sent to the device, previously latched data are discarded and the

last 256 data bytes are guaranteed to be programmed correctly within the same page. If less

than 256 data bytes are sent to device, they are correctly programmed at the requested

addresses without having any effects on the other bytes of the same page.

For optimized timings, it is recommended to use the page program (PP) instruction to

program all consecutive targeted bytes in a single sequence versus using several page

program (PP) sequences with each containing only a few bytes (see Table 17: AC

characteristics).

Chip Select (S) must be driven High after the eighth bit of the last data byte has been

latched in, otherwise the page program (PP) instruction is not executed.

As soon as Chip Select (S) is driven High, the self-timed page program cycle (whose

duration is tPP) is initiated. While the page program cycle is in progress, the status register

may be read to check the value of the write in progress (WIP) bit. The write in progress

(WIP) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. At

some unspecified time before the cycle is completed, the write enable latch (WEL) bit is

reset.

A page program (PP) instruction applied to a page which is protected by the block protect

(BP2, BP1, BP0) bits (see Table 3 and Table 4) is not executed.

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