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M25PX64-STVME6E Datasheet(PDF) 35 Page - Numonyx B.V

Part # M25PX64-STVME6E
Description  64-Mbit, dual I/O, 4-Kbyte subsector erase, serial flash memory with 75 MHz SPI bus interface
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Manufacturer  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

M25PX64-STVME6E Datasheet(HTML) 35 Page - Numonyx B.V

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M25PX64
Instructions
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The protection features of the device are summarized in Table 8.
When the status register write disable (SRWD) bit of the status register is 0 (its initial
delivery state), it is possible to write to the status register provided that the write enable latch
(WEL) bit has previously been set by a write enable (WREN) instruction, regardless of the
whether Write Protect (W/VPP) is driven High or Low.
When the status register write disable (SRWD) bit of the status register is set to ‘1’, two
cases need to be considered, depending on the state of Write Protect (W/VPP):
If Write Protect (W/VPP) is driven High, it is possible to write to the status register
provided that the write enable latch (WEL) bit has previously been set by a write enable
(WREN) instruction.
If write protect (W/VPP) is driven Low, it is not possible to write to the status register
even if the write enable latch (WEL) bit has previously been set by a write enable
(WREN) instruction (attempts to write to the status register are rejected, and are not
accepted for execution). As a consequence, all the data bytes in the memory area that
are software protected (SPM) by the block protect (BP2, BP1, BP0) bits of the status
register, are also hardware protected against data modification.
Regardless of the order of the two events, the hardware protected mode (HPM) can be
entered:
by setting the status register write disable (SRWD) bit after driving Write Protect
(W/VPP) Low
or by driving Write Protect (W/VPP) Low after setting the status register write disable
(SRWD) bit.
The only way to exit the hardware protected mode (HPM) once entered is to pull Write
Protect (W/VPP) High.
If Write Protect (W/VPP) is permanently tied High, the hardware protected mode (HPM) can
never be activated, and only the software protected mode (SPM), using the block protect
(BP2, BP1, BP0) bits of the status register, can be used.
Table 8.
Protection modes
W/VPP
signal
SRWD
bit
Mode
Write protection of
the status register
Memory content
Protected area(1)
1.
As defined by the values in the block protect (BP2, BP1, BP0) bits of the status register, as shown in
Table 3.
Unprotected area(1)
10
Software
protected
(SPM)
Status register is
writable (if the
WREN instruction
has set the WEL
bit)
The values in the
SRWD, BP2, BP1
and BP0 bits can
be changed
Protected against
page program,
sector erase and
bulk erase
Ready to accept
page program and
sector erase
instructions
00
11
01
Hardware
protected
(HPM)
Status register is
hardware write
protected
The values in the
SRWD, BP2, BP1
and BP0 bits
cannot be changed
Protected against
page program,
sector erase and
bulk erase
Ready to accept
page program and
sector erase
instructions


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