M25PE80 datasheet(40/66 Pages) NUMONYX

Part #	M25PE80

Description	8-Mbit, page-erasable serial flash memory with byte alterability, 75 MHz SPI bus, standard pinout

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Manufacturer	NUMONYX [Numonyx B.V]

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Instructions

M25PE80

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6.12

Page erase (PE)

The page erase (PE) instruction sets to ‘1’ (FFh) all bits inside the chosen page. Before it

can be accepted, a write enable (WREN) instruction must previously have been executed.

After the write enable (WREN) instruction has been decoded, the device sets the write

enable latch (WEL).

The page erase (PE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code, and three address bytes on serial data input (D). Any address inside the

page is a valid address for the page erase (PE) instruction. Chip Select (S) must be driven

Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 18.

Chip Select (S) must be driven High after the eighth bit of the last address byte has been

latched in, otherwise the page erase (PE) instruction is not executed. As soon as Chip

Select (S) is driven High, the self-timed page erase cycle (whose duration is tPE) is initiated.

While the page erase cycle is in progress, the status register may be read to check the value

of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed

page erase cycle, and is 0 when it is completed. At some unspecified time before the cycle

is complete, the write enable latch (WEL) bit is reset.

A page erase (PE) instruction applied to a page that is hardware or software protected is not

executed.

Any page erase (PE) instruction, while an erase, program or write cycle is in progress, is

rejected without having any effects on the cycle that is in progress.

If Reset (Reset) is driven Low while a page erase (PE) cycle is in progress, the page erase

cycle is interrupted and the programmed data may be corrupted (see Table 15: Device

status after a Reset Low pulse). On Reset going Low, the device enters the reset mode and

a time of tRHSL is then required before the device can be re-selected by driving Chip Select

(S) Low. For the value of tRHSL see Table 26: Timings after a Reset Low pulse in Section 11:

DC and AC parameters.

Figure 18.

Page erase (PE) instruction sequence

1.

Address bits A23 to A20 are don’t care.

24-bit address

C

D

AI04046

S

2

1

3456789

29 30 31

Instruction

0

23 22

2

0

1

MSB

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