DS18B20

9 of 21

is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Dallas

Semiconductor Touch Memory Products.

CRC GENERATOR Figure 9

1-WIRE BUS SYSTEM

The 1-Wire bus system uses a single bus master to control one or more slave devices. The DS18B20 is

always a slave. When there is only one slave on the bus, the system is referred to as a “single-drop”

system; the system is “multidrop” if there are multiple slaves on the bus.

All data and commands are transmitted least significant bit first over the 1-Wire bus.

The following discussion of the 1-Wire bus system is broken down into three topics: hardware

configuration, transaction sequence, and 1-Wire signaling (signal types and timing).

HARDWARE CONFIGURATION

The 1-Wire bus has by definition only a single data line. Each device (master or slave) interfaces to the

data line via an open-drain or 3-state port. This allows each device to “release” the data line when the

device is not transmitting data so the bus is available for use by another device. The 1-Wire port of the

DS18B20 (the DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 10.

The 1-Wire bus requires an external pullup resistor of approximately 5k

Ω; thus, the idle state for the 1-

Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle

state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-Wire

bus is in the inactive (high) state during the recovery period. If the bus is held low for more than 480

μs,

all components on the bus will be reset.

HARDWARE CONFIGURATION Figure 10

(MSB)

(LSB)

XOR

XOR

XOR

INPUT

4.7k

5μA

Typ.

DS18B20 1-WIRE PORT

100

Ω

MOSFET

1-Wire Bus

DQ

Pin