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CG7C324-A20JC Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CG7C324-A20JC
Description  Reprogrammable Asynchronous CMOS Logic Device
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CG7C324-A20JC Datasheet(HTML) 1 Page - Cypress Semiconductor

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Reprogrammable Asynchronous
CMOS Logic Device
PLDC20RA10
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-03012 Rev. **
Revised March 26, 1997
1PLDC20RA10
Features
• Advanced-user programmable macrocell
• CMOS EPROM technology for reprogrammability
• Up to 20 input terms
• 10 programmable I/O macrocells
• Output macrocell programmable as combinatorial or
asynchronous D-type registered output
• Product-term control of register clock, reset and set and
output enable
• Register preload and power-up reset
• Four data product terms per output macrocell
• Fast
— Commercial
tPD = 15 ns
tCO = 15 ns
tSU = 7 ns
— Military
tPD = 20 ns
tCO = 20 ns
tSU = 10 ns
• Low power
— ICC max - 80 mA (Commercial)
— ICC max = 85 mA (Military)
• High reliability
— Proven EPROM technology
— >2001V input protection
— 100% programming and functional testing
• Windowed DIP, windowed LCC, DIP, LCC, PLCC avail-
able
Functional Description
The Cypress PLDC20RA10 is a high-performance, sec-
ond-generation programmable logic device employing a flexi-
ble macrocell structure that allows any individual output to be
configured independently as a combinatorial output or as a
fully asynchronous D-type registered output.
The Cypress PLDC20RA10 provides lower-power operation
with superior speed performance than functionally equivalent
bipolar devices through the use of high-performance 0.8-mi-
cron CMOS manufacturing technology.
The PLDC20RA10 is packaged in a 24 pin 300-mil molded
DIP, a 300-mil windowed cerDIP, and a 28-lead square lead-
less chip carrier, providing up to 20 inputs and 10 outputs.
When the windowed device is exposed to UV light, the 20RA10
is erased and can then be reprogrammed.
Logic Block Diagram
4
98
7
6
5
432
1
10
15
16
17
18
19
20
21
22
23
24
I
I
II
II
I
I
4
4
4
4
4
4
4
VCC
11
12
13
14
I
VSS
OE
4
4
I
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
4
4
4
4
4
4
4
4
44
MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
9
8
7
6
5
4
321
0
PL
RA10–1


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