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ONET4211LDRGER Datasheet(PDF) 6 Page - Texas Instruments |
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ONET4211LDRGER Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 26 page  www.ti.com PACKAGE ONET4211LD SLLS688 – NOVEMBER 2005 DETAILED DESCRIPTION (continued) Table 1. Response to I/O-Pin Shorts to VCC or GND FLTMODE = LOW FLTMODE = HIGH PIN Response to Short to GND Response to Short to VCC Response to Short to GND Response to Short to VCC APCSET SDOWN latched high, IBIAS and No fault, IMOD unaffected SDOWN high, IBIAS and IMOD No fault IMOD disabled unaffected BIAS SDOWN latched high, IMOD No fault, IBIAS goes to zero SDOWN high, IMOD No fault, IMOD unaffected disabled unaffected CAPC No fault No fault, IBIAS goes to zero No fault, IMOD unaffected No fault, IBIAS goes to zero DIN+ No fault, IMOD disabled No fault No fault, IMOD disabled No fault DIN– No fault, IMOD disabled No fault No fault, IMOD disabled No fault DISABLE Normal circuit operation Normal circuit operation Normal circuit operation Normal circuit operation IBMAX SDOWN latched high, IBIAS and SDOWN latched high, IBIAS SDOWN high, IMOD SDOWN high, IMOD unaffected IMOD disabled and IMOD disabled unaffected MOD+ SDOWN latched high, IBIAS and No fault SDOWN high, IBIAS No fault IMOD disabled unaffected MOD– SDOWN latched high, IBIAS and No fault SDOWN high, IBIAS No fault IMOD disabled unaffected MODSET SDOWN latched high, IBIAS and No fault, IMOD disabled SDOWN high, IBIAS No fault, IMOD disabled IMOD disabled unaffected MODTC SDOWN latched high, IBIAS and No fault SDOWN high, IBIAS and IMOD No fault IMOD disabled unaffected MONB No fault SDOWN latched high, IBIAS No fault SDOWN high, IBIAS and IMOD and IMOD disabled unaffected MONP No fault SDOWN latched high, IBIAS No fault SDOWN high, IBIAS and IMOD and IMOD disabled unaffected OUTPOL No fault, polarity reverses No fault No fault, polarity reverses No fault PD No fault, IMOD unaffected No fault, IBIAS goes to zero No fault, IMOD unaffected No fault, IBIAS goes to zero SDOWN No fault No fault No fault No fault For the ONET4211LD, a small-footprint, 4-mm × 4-mm, 24-lead QFN package is used, with a lead pitch of 0,5 mm. The pinout is shown in Figure 3. To achieve the required low thermal resistance of about 38 K/W, which keeps the maximum junction temperature below 115 °C, a good thermal connection of the exposed die pad is mandatory. 6 |
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