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TLV1578 Datasheet(PDF) 7 Page - Texas Instruments |
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TLV1578 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 33 page TLV1571, TLV1578 2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTERS SLAS170D –MARCH 1999 – REVISED JULY 2000 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description (continued) configure the device The device can be configured by writing to control registers CR0 and CR1. Table 2. TLV1571/TLV1578 Programming Examples REGISTER INDEX D7 D6 D5 D4 D3 D2 D1 D0 COMMENT REGISTER D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 COMMENT EXAMPLE1 CR0 0 0 0 0 0 0 0 0 0 0 Single channel CR1 0 1 0 0 0 0 0 1 0 0 Single Input EXAMPLE2 CR0 0 0 0 1 1 0 1 0 1 1 Sweep mode CR1 0 1 0 0 0 0 1 1 0 0 2s complement output register read back Control data written to the TLV1571/78 can be read back from the control registers CR0 and CR1. See Figure 2. NOTE: Data read out of CR1 reserved bits is don’t care. power down The TLV1571/TLV1578 offers two power down modes, auto power down and software power down. This device will automatically proceed to auto power-down mode if RD is not present one clock after conversion. Software power down is controlled directly by the user by pulling CS to DVDD. Table 3. Power Down Modes PARAMETERS/MODES AUTO POWER DOWN SOFTWARE POWER DOWN (CS = DVDD) Maximum power down dissipation current 1 mA 10 µA Comparator Power down Power down Clock buffer Power down Power down Reference Active Power down Control registers Saved Saved Minimum power down time 1 CLK 2 CLK Minimum resume time 1 CLK 2 CLK self-test modes The TLV1571/TLV1578 provides three self test modes. These modes can be used to check whether the ADC itself is working properly without having to supply an external signal. There are three tests that are controlled by writing to CR1(D1,D0) (see Table 4). Table 4. Self Tests CR1(D1,D0) SELF TEST VOLTAGE APPLIED DIGITAL OUTPUT 0h Normal, no self test applied N/A 1h VREFM applied to ADC input internally 000h 2h (VREFP–VREFM)/2 applied to ADC input internally 200h 3h VIN = VREFP applied to ADC input internally 3FFh |
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