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LIS1R02 Datasheet(PDF) 6 Page - STMicroelectronics |
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LIS1R02 Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 11 page ![]() LIS1R02 (L6671) 6/11 The FIFO has four registers grouped into two banks. The first bank consists of the first and the second register. The first register is the one written first since the last read. The second bank consists of the third and fourth register. 0000: address for the first bank 0010: address for the second bank The device puts out first the data of the first register of the bank with the MSB first. 2.0 LIS1R02 REGISTERS The registers are grouped into two banks. The following table summarizes their mapping. 2.1 Registers Bank 0 AD(3:0) = 0100 CTRL_Reg1 This is the first control register. It has 8 bit whose function is summarized below. Note: x means don't care value. Note: default value after Power On Reset is 0100 0000 1xxx xxxx Chip in Power Down mode xx00 xxxx Clock from CLK pin xx01 xxxx Clock derived from the internal oscillator xx10 xxxx Clock from the PLL locking on CLK_in xx11 xxxx Clock from the PLL locking on FIFO_Low reading xxxx 1xxx Internal Oscillator in Power Down mode Address Reg. Bank 0 Reg. Bank 1 0000 FIFO_Low FIFO_Low 0001 not used not used 0010 FIFO_High FIFO_High 0011 not used not used 0100 CTRL_Reg1 CTRL_Reg1 0101 CTRL_Reg2 CTRL_Reg2 0110 PLL_PRESC_MULT FLASH_Reg1 0111 PLL_MULT FLASH_Reg2 1000 IIR_A0 GAIN_Low 1001 IIR_A1 GAIN_High 1010 IIR_A2 OFFSET_Low 1011 IIR_B1 OFFSET_High 1100 IIR_B2 CURR_BANDGAP 1101 IIR_SIGN_BIT BAND_CSACT_Reg 1110 DSC_Reg CS_TRIM 1111 MISC_Reg MISC_Reg |
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