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F_USB20LP Datasheet(PDF) 1 Page - Fujitsu Component Limited.

Part No. F_USB20LP
Description  Standard Bus IP: High Speed USB 2.0 Device Controller
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Maker  FUJITSU [Fujitsu Component Limited.]
Homepage  http://edevice.fujitsu.com/fmd/en/index.html
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Standard Bus IP: High Speed USB 2.0 Device Controller
Supports high-speed (480Mbps) and full-speed (12Mbps)
Customize endpoint numbers and configurations
UTMI (USB2.0 Transceiver Macrocell Interface)
Features
Full compliance with USB 2.0 Device Controller standard
Integrated PHY macro for system cost reduction and space saving
End-Point
FIFO
Control
Status
Register
USB
LINK
UTMI
PHY
Fujitsu Macro
F_USB20LP
Interrupt
Fujitsu USB 2.0 device controller is a synthesizable core suitable
for different process. Corresponding physical interface in 0.18um
and 0.11um technology (supporting high and full speed operation)
also available for integration.
Generic CPU interface makes it easy to be integrated into overall
ASIC. Different endpoints are available for application such as
printer, scanner, digital still camera, bluetooth devices, digital set
top box,cable modems and PC Access Point to high speed wireless
connectivity.
Integrated SIE performs synchronization pattern recognition, bit
stuffing/ stripping, CRC check/ generation, serial/ parallel conversion,
PID verification, address recognition and handshake evaluation/
response.
The macro decodes and handles standard USB commands. Device
class specific command is passed on to the ASIC for further
processing.
Overview
Link
Protocol Engine (UDC-20) is a fully synthesizable soft core that
supports high-speed (480 Mbps), full-speed (12Mbps) signaling
bit rates.
Protocol engine reduces CPU burden by processing basic USB
2.0 protocols in hardware.
Endpoint numbers, configurations, and its FIFO densities
are flexible. Following is one of the configuration examples.
1) End Point 0 control out
2) End Point 0 control in
3) End Point 1 Bulk out
4) End Point 2 Bulk in
5) End Point 3 Interrupt in
64Byte
64Byte
512Byte (Double buffer)
512Byte (Double buffer)
64Byte
Description
PHY block consists of a 0.18um hard macro and a soft macro
(Receiving Block).
PHY block supports high-speed (480Mbps) and full-speed (12Mbps).
Contains high-speed Analog Blocks and high-speed SERDES
(serializer and de-serializer Logic) and provides a parallel interface
to UDC-20 protocol Engine.
16bit parallel connection to Link
PHY




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