FS791/92/94
Document #: 38-07343 Rev *A
Page 3 of 9
Absolute Maximum Ratings[1, 2]
Parameter
Description
Min.
Max.
Unit
VDD
Operating Voltage
3.0
6.0
VDC
VIRVSS
Input, relative to VSS
–0.3
VDD + 0.3
VDC
VORVSS
Output, relative to VSS
–0.3
VDD + 0.3
VDC
∆V
PP
AVDD relative to DVDD
–100
+100
mV
∆V
SS
AVSS relative to DVSS
–100
+100
mV
TOP
Temperature, operating
0
+70
°C
TST
Temperature, Storage
–65
+150
°C
Table 2. DC Electrical Characteristics: Test measurements performed at VDD = 3.3V and 5.0V ±10%, Xin = 100 MHz, Ta =
0°C to 70°C
Parameter
Description
Min.
Typ.
Max.
Unit.
VIL
Input Low Voltage
0.8
VDC
VIH
Input High Voltage
2.0
VDC
IIL
Input Low Current
100
µA
IIH
Input High Current
100
µA
VOL
Output Low Voltage IOL= 10 mA, VDD = 5V
0.4
VDC
VOH
Output High Voltage IOH = 10 mA, VDD = 5V
VDD – 1.0
VDC
VOL
Output Low Voltage IOL = 6 mA, VDD = 3.3V
0.4
VDC
VOH
Output High Voltage IOH = 5 mA, VDD = 3.3V
2.4
VDC
Cin1
Input Capacitance (Pin-1)
6
8
10
pF
Cin2
Output Capacitance (Pin-2)
6
8
10
pF
ICC
5-Volt Dynamic Supply Current (CL = O)
45
55
mA
ICC
3.3-Volt Dynamic Supply Current (CL = O)
22
28
mA
ISC
Short Circuit Current (FM-OUT)
25
VDC
Table 3. Timing Characteristics: Test measurements performed at VDD = 3.3V and 5.0V ±10%, Ta = 0°C to 70°C, CL = 20 pF,
Xin = 100 MHz
Parameter
Description
Min.
Typ.
Max.
Unit
tTLH
Output Rise Time Measured at 10% - 90% @ 5 VDC
2.0
2.2
2.5
ns
tTHL
Output Fall Time Measured at 10% - 90% @ 5 VDC
1.7
2.0
2.2
ns
tTLH
Output Rise Time Measured at 0.8V - 2.0V @ 5 VDC
0.50
0.65
0.75
ns
tTHL
Output Fall Time Measured at 0.8V - 2.0 V @ 5 VDC
0.50
0.65
0.75
ns
tTLH
Output Rise Time Measured at 10% - 90% @ 3.3 VDC
2.60
2.65
2.90
ns
tTHL
Output Fall Time Measured at 10% - 90% @ 3.3 VDC
2.00
2.10
2.20
ns
tTLH
Output Rise Time Measured at 0.8V - 2.0V @ 3.3 VDC
0.80
0.95
1.10
ns
tTHL
Output Fall Time Measured at 0.8V - 2.0 V @ 3.3 VDC
0.78
0.85
0.90
ns
TsymF1
Output Duty Cycle
45
50
55
%
tj1s
Peak-to Peak Jitter One Sigma
-
150
250
ps
Note:
1.
Single Power Supply: The voltage on any input or I/O pin cannot excceed the power pin during power-up.
2.
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions should be taken to avoid
application of any voltage higher than the absolute maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the
range, VSS < (Vin or Vout) < VDD. All digital inputs are tied HIGH or LOW internally. Refers to electrical specifications for operating supply range.
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