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PRELIMINARY
CYU01M16SCCU
MoBL3™
Document #: 38-05601 Rev. *B
Page 6 of 12
Write Cycle[15]
tWC
Write Cycle Time
70
40000
ns
tSCE
CE LOW to Write End
60
ns
tAW
Address Set-Up to Write End
60
ns
tCD
Chip Deselect Time CE1 = HIGH or
CE2 =LOW, BLE/BHE High Pulse Time
15
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
50
ns
tBW
BLE/BHE LOW to Write End
60
ns
tSD
Data Set-Up to Write End
25
ns
tHD
Data Hold from Write End
0
ns
tHZWE
WE LOW to High-Z[10, 11, 12]
25
ns
tLZWE
WE HIGH to Low-Z[10, 11, 12]
10
ns
Note:
15. The internal Write time of the memory is defined by the overlap of WE,CE1 = VIL or CE2 = VIH, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the write
Switching Characteristics Over the Operating Range[9, 10, 11, 15,14] (continued)
Parameter
Description
70 ns
Unit
Min.
Max.
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