CYW15G0201DXB
CYV15G0201DXB
CYP15G0201DXB
Document #: 38-02058 Rev. *H
Page 10 of 46
REFCLK
±
Differential LVPECL
or single-ended
LVTTL input clock
Reference Clock. This clock input is used as the timing reference for the transmit and
receive PLLs. This input clock may also be selected to clock the transmit and receive parallel
interfaces. When driven by a single-ended LVCMOS or LVTTL clock source, connect the
clock source to either the true or complement REFCLK input, and leave the alternate
REFCLK input open (floating). When driven by an LVPECL clock source, the clock must be
a differential clock, using both inputs. When TXCKSEL = LOW, REFCLK is also used as the
clock for the parallel transmit data (input) interface. When RXCKSEL = LOW, the Elasticity
Buffer is enabled and REFCLK is used as the clock for the parallel receive data (output)
interface.
If the Elasticity Buffer is used, framing characters will be inserted or deleted to/from the data
stream to compensate for frequency differences between the reference clock and recovered
clock. When addition happens, a K28.5 will be appended immediately after a framing
character is detected in the Elasticity Buffer. When deletion happens, a framing character
will be removed from the datastream when detected in the Elasticity Buffer.
RXCLKC+
3-state LVTTL
Output
Delayed REFCLK+ when RXCKSEL=LOW. Delayed form of REFCLK+, used for transfer
of recovered data to a host system. This output is only enabled when the receive parallel
interface is configured to present data relative to REFCLK (RXCKSEL = LOW).
SPDSEL
3-Level Select[4],
static control input
Serial Rate Select. This input specifies the operating bit-rate range of both transmit and
receive PLLs. LOW = 195–400 MBaud, MID = 400–800 MBaud, HIGH = 800–1500 MBaud
(800–1540 MBaud for CYW15G0201DXB). When SPDSEL is LOW, setting TXRATE =
HIGH (Half-rate Reference Clock) is invalid.
TRSTZ
LVTTL Input,
internal pull-up
Device Reset. Active LOW. Initializes all state machines and counters in the device.
When sampled LOW by the rising edge of REFLCK, this input resets the internal state
machines and sets the Elasticity Buffer pointers to a nominal offset. When the reset is
removed (TRSTZ sampled HIGH by REFCLK
↑), the status and data outputs will become
deterministic in less than 16 REFCLK cycles.
The BISTLE, OELE, and RXLE latches are reset by TRSTZ.
If the Elasticity Buffer or the Phase Align Buffer are used, TRSTZ should be applied after
power up to initialize the internal pointers into these memory arrays.
Analog I/O and Control
OUTA1
±
OUTB1
±
CML Differential
Output
Primary Differential Serial Data Outputs. These PECL-compatible CML outputs (+3.3V
referenced) are capable of driving terminated transmission lines or standard fiber-optic
transmitter modules.
OUTA2
±
OUTB2
±
CML Differential
Output
Secondary Differential Serial Data Outputs. These PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard
fiber-optic transmitter modules.
INA1
±
INB1
±
LVPECL Differential
Input
Primary Differential Serial Data Inputs. These inputs accept the serial data stream for
deserialization and decoding. The INx1
± serial streams are passed to the receiver Clock
and Data Recovery (CDR) circuits to extract the data content when INSELx = HIGH.
INA2
±
INB2
±
LVPECL Differential
Input
Secondary Differential Serial Data Inputs. These inputs accept the serial data stream for
deserialization and decoding. The INx2
± serial streams are passed to the receiver Clock
and Data Recovery (CDR) circuits to extract the data content when INSELx = LOW.
INSELA
INSELB
LVTTL Input,
asynchronous
Receive Input Selector. Determines which external serial bit stream is passed to the
receiver Clock and Data Recovery circuit. When HIGH, the INx1
± input is selected. When
LOW, the INx2
± input is selected.
SDASEL
3-Level Select [4],
static configuration
input
Signal Detect Amplitude Level Select. Allows selection of one of three predefined
amplitude trip points for a valid signal indication, as listed in Table 11.
LPEN
LVTTL Input,
asynchronous,
internal pull-down
All-Port Loop-Back-Enable. Active HIGH. When asserted (HIGH), the transmit serial data
from each channel is internally routed to the associated receiver Clock and Data Recovery
(CDR) circuit. All serial drivers are forced to differential logic “1”. All serial data inputs are
ignored.
Pin Descriptions CYP(V)(W)15G0201DXB Dual HOTLink II Transceiver (continued)
Pin Name
I/O Characteristics
Signal Description
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