CYW15G0201DXB
CYV15G0201DXB
CYP15G0201DXB
Document #: 38-02058 Rev. *H
Page 6 of 46
Pin Descriptions CYP(V)(W)15G0201DXB Dual HOTLink II Transceiver
Pin Name
I/O Characteristics
Signal Description
Transmit Path Data Signals
TXPERA
TXPERB
LVTTL Output,
changes relative to
REFCLK
↑ [3]
Transmit Path Parity Error. Active HIGH. Asserted (HIGH) if parity checking is enabled
and a parity error is detected at the Encoder. This output is HIGH for one transmit character
clock period to indicate detection of a parity error in the character presented to the Encoder.
If a parity error is detected, the character in error is replaced with a C0.7 character to force
a corresponding bad-character detection at the remote end of the link. This replacement
takes place regardless of the encoded/non-encoded state of the interface.
When BIST is enabled for the specific transmit channel, BIST progress is presented on
these outputs. Once every 511 character times (plus a 16-character Word Sync Sequence
when the receive channels are clocked by a common clock, i.e., RXCKSEL = LOW or
HIGH), the associated TXPERx signal pulses HIGH for one transmit-character clock period
(if RXCKSEL = MID) or seventeen transmit- character clock periods (if RXCKSEL = LOW
or HIGH) to indicate a complete pass through the BIST sequence. For RXCKSEL = LOW
or HIGH, if TXMODE[1:0] = LL, then no Word Sync Sequence is sent in BIST, and TXPERx
pulses HIGH for one transmit-character clock period.
These outputs also provide indication of a transmit Phase-Align Buffer underflow or
overflow. When the transmit Phase-Align Buffers are enabled (TXCKSEL
≠ LOW, or
TXCKSEL = LOW and TXRATE = HIGH), if an underflow or overflow condition is detected,
TXPERx for the channel in error is asserted and remains asserted until either an atomic
Word Sync Sequence is transmitted or TXRST is sampled LOW to re-center the transmit
Phase-Align Buffers.
TXCTA[1:0]
TXCTB[1:0]
LVTTL Input,
synchronous,
sampled by the
selected TXCLKx
↑
or REFCLK
↑ [3]
Transmit Control. These inputs are captured on the rising edge of the transmit interface
clock as selected by TXCKSEL, and are passed to the Encoder or Transmit Shifter. They
identify how the associated TXDx[7:0] characters are interpreted. When the Encoder is
bypassed, these inputs are interpreted as data bits. When the Encoder is enabled, these
inputs determine if the TXDx[7:0] character is encoded as Data, a Special Character code,
or replaced with other Special Character codes. See Table 1 for details.
TXDA[7:0]
TXDB[7:0]
LVTTL Input,
synchronous,
sampled by the
selected TXCLKx
↑
or REFCLK
↑ [3]
Transmit Data Inputs. These inputs are captured on the rising edge of the transmit
interface clock (selected by TXCKSEL) and passed to the Encoder or Transmit Shifter.
When the Encoder is enabled (TXMODE[1:0]
≠ LL), TXDx[7:0] specify the specific data or
command character to be sent.
When the Encoder is bypassed, these inputs are interpreted as data bits of the 10-bit input
character. See Table 1 for details.
TXRST
LVTTL Input,
asynchronous,
internal pull-up,
REFCLK
↑ [3]
Transmit Clock Phase Reset. Transmit Clock Phase Reset. Active LOW. When sampled
LOW, the transmit Phase-align Buffers are allowed to adjust their data-transfer timing
(relative to the selected input clock) to allow clean transfer of data from the Input Register
to the Encoder or Transmit Shifter. When TXRST is sampled HIGH, the internal phase
relationship between the associated TXCLKx and the internal character-rate clock is fixed
and the device operates normally.
When configured for half-rate REFCLK sampling of the transmit character stream
(TXCKSEL = LOW and TXRATE = HIGH), assertion of TXRST is only used to clear
Phase-align buffer faults caused by highly asymmetric REFCLK periods or REFCLKs with
excessive cycle-to-cycle jitter. During this alignment period, one or more characters may be
added to or lost from all the associated transmit paths as the transmit Phase-align Buffers
are adjusted. TXRST must be sampled LOW by a minimum of two consecutive rising edges
of REFCLK to ensure the reset operation is initiated correctly on all channels. This input is
ignored when both TXCKSEL and TXRATE are LOW, since the phase align buffer is
bypassed. In all other configurations, TXRST should be asserted during device initialization
to ensure proper operation of the Phase-align buffer. TXRST should be asserted after
presence of a valid TXCLKx and after allowing enough time for the TXPLL to lock to the
reference clock (as specified by parameter tTXLOCK).
Note:
3.
When REFCLK is configured for half-rate operation (TXRATE = HIGH), these inputs are sampled (or the outputs change) relative to both the rising and falling
edges of REFCLK.
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