CYDM256A16, CYDM128A16,
CYDM064A16, CYDM128A08,
CYDM064A08
Document #: 38-06081 Rev. *F
Page 7 of 25
guarantee which side will control the semaphore. On
power-up, both ports should write “1” to all eight semaphores.
Architecture
The
CYDM256A16,
CYDM128A16,
CYDM064A16,
CYDM128A08, CYDM064A08 consist of an array of 4K, 8K,
or 16K words of 16 dual-port RAM cells, I/O and address lines,
and control signals (CE, OE, R/W). The CYDM064A08 and
CYDM128A08 consist of an array of 8K and 16K words of 8
each of dual-port RAM cells, I/O and address lines, and control
signals (CE, OE, R/W).These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two Interrupt (INT) pins can be utilized
for port-to-port communication. Two Semaphore (SEM)
control pins are used for allocating shared resources. With the
M/S pin, the devices can function as a master (BUSY pins are
outputs) or as a slave (BUSY pins are inputs). The devices
also have an automatic power-down feature controlled by CE.
Each port is provided with its own output enable control (OE),
which allows data to be read from the device.
Notes:
14. This column applies to x16 devices only.
15. See Interrupts Functional Description for specific highest memory locations by device.
16. If BUSYR = L, then no change.
17. If BUSYL = L, then no change.
18. See Functional Description for specific addresses by device.
19. SFEN = VIL for IRR reads
20. UB or LB = VIL. If LB = VIL, then DQ<7:0> are valid. If UB = VIL then DQ<15:8> are valid.
21. LB must be active (LB = VIL) for these bits to be valid.
22. SFEN active when either CEL = VIL or CER = VIL. It is inactive when CEL = CER = VIH.
Table 1. Non-Contending Read/Write
Inputs
Outputs
Operation
CE
R/W
OE
UB
LB
SEM
I/O8–I/O15[14] I/O0–I/O7
H
X
X
X
X
H
High Z
High Z
Deselected: Power-down
X
X
X
H
H
H
High Z
High Z
Deselected: Power-down
L
L
X
L
H
H
Data In
High Z
Write to Upper Byte Only
L
L
X
H
L
H
High Z
Data In
Write to Lower Byte Only
L
L
X
L
L
H
Data In
Data In
Write to Both Bytes
L
H
L
L
H
H
Data Out
High Z
Read Upper Byte Only
L
H
L
H
L
H
High Z
Data Out
Read Lower Byte Only
L
H
L
L
L
H
Data Out
Data Out
Read Both Bytes
X
X
H
X
X
X
High Z
High Z
Outputs Disabled
H
H
L
X
X
L
Data Out
Data Out
Read Data in Semaphore Flag
X
H
L
H
H
L
Data Out
Data Out
Read Data in Semaphore Flag
H
X
X
X
L
Data In
Data In
Write DIN0 into Semaphore Flag
X
X
H
H
L
Data In
Data In
Write DIN0 into Semaphore Flag
LX
XLXL
Not Allowed
L
X
X
X
L
L
Not Allowed
Table 2. Interrupt Operation Example (Assumes BUSYL = BUSYR = HIGH)[15]
Function
Left Port
Right Port
R/WL
CEL
OEL
A0L–13L
INTL R/WR CER
OER
A0R–13R
INTR
Set Right INTR Flag
L
L
X
3FFF[18]
XX
XX
X
L[17]
Reset Right INTR Flag
X
X
XXX
X
L
L
3FFF[18]
H[16]
Set Left INTL Flag
X
X
X
X
L[16]
LL
X
3FFE[18]
X
Reset Left INTL Flag
X
L
L
3FFE[18]
H[17]
X
X
XXX
Table 3. Input Read Register Operation[19, 22]
SFEN
CE
R/W
OE
UB
LB
ADDR
I/O0–I/O1 I/O2–I/O15
Mode
HLHL
L
L
x0000-Max VALID[20] VALID[20] Standard Memory Access
L
L
H
L
X
L
x0000
VALID[21]
X
IRR Read
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