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CYNSE10512 Datasheet(PDF) 23 Page - Cypress Semiconductor

Part # CYNSE10512
Description  Ayama??10000 Network Search Engine
Download  153 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYNSE10512 Datasheet(HTML) 23 Page - Cypress Semiconductor

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CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 23 of 153
CLK2X runs at twice the frequency of CLK1X. “A” refers to the first CLK2X cycle in a CLK1X cycle. “B” refers to the second CLK2X
cycle in a CLK1X cycle.
When MultiSearch is issued on x72 tables, Array 0 will use the GMR provided in cycle 1 and Array 1 will automatically selects to
use the next-up GMR. For example, if GMR[0] is selected in cycle 1, GMR[1] will be selected automatically for Array 1. Array 0
uses the Search key provided in cycle 1-A while Array 1 uses the Search key provided in cycle 1-B.
When MultiSearch is issued on x288 tables, Array 0 and Array 1 will both use the same Search key selected in cycle 1 and cycle 2.
The GMR selection for Array 0 is done per cycle and Array 1 automatically selects the next up GMR register. For example, if
GMR[6] is selected for the first 144 bits of Array 0 in cycle 1, GMR[7] is automatically selected for the first 144 bits of Array 1.
Then if GMR[15] is selected for the second 144 bits of Array 0 in cycle 2, GMR[0] is automatically selected for the second 144
bits of Array 1.
In all cases, the CMPR used in the Search operation for Array 0 is the one selected in cycle 1 and the next up CMPR is
automatically selected for Array 1.
Internal register for configuration: CMD.
5.1.2.5 Enhanced Learn Operation
Ayama 10000 extends the capability of the Learn function to allow users to select the data source for the operation. The data can
be from the DQ bus or one of the Comparand (CMPR) registers. It also allows the data to be written to both the mask and data
array while in Non-Enhanced mode it allows the data to be written only to the data array.
Internal register for configuration: CMD.
5.2
I/O Interfaces
Data flows in and out of the device through three separate I/O interfaces: ASIC, SRAM and Cascade Interface. Section 4.0,
“Signals Description,” on page 15 lists the signals that are part of each interface. Input signals are registered on the rising edge
and falling edge of CLK1X or rising edge of CLK2X. Output signals are driven out on the rising edge of CLK1X or rising edge of
CLK2X when PHS_L is Low. An exception is when MultiSearch operation is activated, the output will be driven out on both edges
of CLK1X or rising edge of CLK2X. Refer to Section 5.6 for more information on clock signals. Figure 5-7 shows an example of
ASIC, NSEs and SRAMs I/O interconnects. The SRAM Interface outputs may be connected to SRAM devices in associative
applications mode or back to the ASIC in index applications mode.
Table 5-2. Selection of Search Key, GMR, and CMPR in MultiSearch Operation
Search Width
Array 0
Array 1
GMR
Key
SRR
GMR
Key
SRR
x72/x72
1: GMR
1: A
1: CMPR
1: GMR+1
1: B
1: CMPR+1
x144/x144
1: GMR
1: A, B
1: CMPR
1: GMR+1
1: A, B
1: CMPR+1
x288/x288
1: GMR
1: A, B
1: CMPR
1: GMR+1
1: A, B
1: CMPR+1
2: GMR
2: A, B
2: GMR+1
2: A, B
x576/x576
1: GMR
1: A, B
1: CMPR
1: GMR+1
1: A, B
1: CMPR+1
2: GMR
2: A, B
2: GMR+1
2: A, B
3: GMR
3: A, B
3: GMR+1
3: A, B
4: GMR
4: A, B
4: GMR+1
4: A, B
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