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CYNSE10512 Datasheet(PDF) 11 Page - Cypress Semiconductor

Part # CYNSE10512
Description  Ayama??10000 Network Search Engine
Download  153 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYNSE10512 Datasheet(HTML) 11 Page - Cypress Semiconductor

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CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 11 of 153
2.0
Overview
Cypress Semiconductor Corporation’s (Cypress’s) Ayama™ 10000 Network Search Engine (NSE) is designed to be a high-
performance, pipelined, synchronous, 512K/256K/128K 36-bit entries NSE. This high-speed, high-capacity Ayama 10000 NSE
can be deployed in a variety of networking and communications applications. It can be used to accelerate network protocols such
as Longest-Prefix Match (CIDR), ARP, MPLS, and other layer 2, 3, and 4 protocols. The performance and features of the
Ayama 10000 make it attractive in applications such as Enterprise LAN switches and routers, and broadband switching and/or
routing equipment that supports multiple data rates at OC–48 and beyond. Ayama 10000 can operate at a maximum performance
of 266 million searches per second (MSPS).
The Ayama 10000 is designed to be scalable in order to support network database sizes of up to 15872K 36-bit entries specifically
for environments that require large network policy databases. It includes features that ease table management, reduce power
consumption and improve data integrity. The device can have its features individually enabled or disabled for flexibility based on
the needs of the applications. The Ayama 10000’s Data and Mask arrays that make up the Core are organized into blocks that
can be individually configured to optimize the device performance and provide even more flexibility.
Figure 2-1 below shows the block diagram of the Ayama 10000.
Compare / PIO Data
DQ[71:0]
CMDV
CMD[10:0]
LHI[6:0]/LHI_0[6:0]
Command
PIO Access
CMD
Arbitration
Logic
LHO[1:0]/LHO_0[1:0]
and
SRAM
Interface
SADR[N:0],
OE_L
BHO[2:0]
SSF
WE_L
CE_L
ID[4:0]
BHI[2:0]
SSV
ACK
TAP
ALE_L
FULO[1:0]/LHO_1[1:0]
FULI[6:0]/LHI_1[6:0]
EOT
Full Logic
FULL
RST_L
PHS_L
Decode
CLK1X/CLK2X
Mask Array
Data Array
CLK_MODE
Block Associated
Internal Registers
Figure 2-1. Ayama™ 10000 Block Diagram
Control
Control and Configuration
Pipeline
Internal Registers
PAR[1:0]
PARERR_L
Controller
TMS
TDI
TCK
TRST_L
TDO
MULTI_HIT
N = 25 for
CYNSE10512,
24 for
23 for
CYNSE10256,
CYNSE10128
Parity
and
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