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CYNSE10512 Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # CYNSE10512
Description  Ayama??10000 Network Search Engine
Download  153 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYNSE10512 Datasheet(HTML) 8 Page - Cypress Semiconductor

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CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 8 of 153
LIST OF TABLES
Table 3-1. Bit Position Match ................................................................................................................14
Table 4-1. Ayama™ 10000 Signal Description .....................................................................................15
Table 5-1. Summary of Non-Enhanced and Enhanced Mode Features and Functions Differences ....18
Table 5-2. Selection of Search Key, GMR, and CMPR in MultiSearch Operation ................................23
Table 5-3. List of Internal Registers ......................................................................................................25
Table 5-4. Search Successful Register Description .............................................................................28
Table 5-5. Command Register Description ...........................................................................................28
Table 5-6. Information Register Description .........................................................................................30
Table 5-7. Read Burst Register Description .........................................................................................30
Table 5-8. Write Burst Register Description .........................................................................................31
Table 5-9. NFA Register Description ....................................................................................................31
Table 5-10. Configuration Register Description ....................................................................................32
Table 5-11. Hardware Register Description ..........................................................................................33
Table 5-12. Parity Control Register Description ...................................................................................34
Table 5-13. Control Register .................................................................................................................35
Table 5-14. Search Result Register ......................................................................................................36
Table 5-15. SRR’s INDEX Composition Based on STATUS ................................................................36
Table 5-16. Block Mini-Key Register Description .................................................................................37
Table 5-17. Block Priority Register Description ....................................................................................38
Table 5-18. Block Parity Register Description ......................................................................................39
Table 5-19. Block NFA Register Description ........................................................................................39
Table 5-20. Block Priority Register Alias for Priority #0 Fields .............................................................41
Table 5-21. Block Priority Register Alias for Priority #1 Fields .............................................................41
Table 5-22. Block Priority Register Alias for Priority #2 Fields .............................................................41
Table 5-23. Block Priority Register Alias for Priority #3 Fields .............................................................41
Table 5-24. Pipeline Stages and Maximum Operating Speed. .............................................................43
Table 5-25. Data Array, Mask Array and External SRAM Address Space Encoding ...........................44
Table 5-26. SRAM Address Generation ...............................................................................................44
Table 5-27. Internal Register Address Space Encoding .......................................................................45
Table 5-28. Cascadability of Operations and Features ........................................................................45
Table 6-1. Command Codes .................................................................................................................50
Table 6-2. Single/Burst Read Command Parameters ..........................................................................51
Table 6-3. Single/Burst Write Command Parameters ...........................................................................54
Table 6-4. TLSZ[1:0] Description ..........................................................................................................56
Table 6-5. Shift of SSF and SSV from SADR .......................................................................................58
Table 6-6. Hit/Miss Assumptions ..........................................................................................................61
Table 6-7. Hit/Miss Assumption for MultiSearch Mode .........................................................................67
Table 6-8. Hit/Miss Assumptions ..........................................................................................................72
Table 6-9. Hit/Miss Assumptions ..........................................................................................................85
Table 6-10. Hit/Miss Assumptions for 576-bit Multi Search ..................................................................90
Table 6-11. Hit/Miss Assumptions ........................................................................................................95
Table 6-12. Hit/Miss Assumptions in MultiSearchMode .....................................................................108
Table 6-13. SRAM Write Cycle Latency from Second Cycle of Learn Instruction ..............................120
Table 6-14. Required Idle Cycles Between Commands .....................................................................133
Table 7-1. Supported Operations .......................................................................................................135
Table 7-2. TAP Device ID Register .....................................................................................................135
Table 9-1. DC Electrical Characteristics for Ayama 10000 .................................................................137
Table 9-2. Operating Conditions for Ayama 10000 ............................................................................137
Table 10-1. AC Timing Parameters with CLK2X ................................................................................138
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