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CYNSE10512 Datasheet(PDF) 64 Page - Cypress Semiconductor

Part # CYNSE10512
Description  Ayama??10000 Network Search Engine
Download  153 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYNSE10512 Datasheet(HTML) 64 Page - Cypress Semiconductor

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CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 64 of 153
The following is the sequence of operation for a single 72-bit Search command (also refer to Subsection 6.2, “Command Bus
Parameters,” on page 50).
• Cycle A:
— Command Bus: The host ASIC drives CMDV HIGH and applies Search command CMD[1:0] = “10”. The CMD[2] and
CMD[9] signals must be driven to logic 0 for this 72-bit search. {CMD[10],CMD[5:3]} signals must be driven with the index
to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same bits that will be driven on
SADR[25:23] for CYNSE10512, SADR[24:22] for CYNSE10256, SADR[23:21] for CYNSE10128 by this device if it has a hit.
— DQ Bus: At the same time in cycle A, DQ[71:0] must be driven with the 72-bit data to be compared.
• Cycle B:
— Command Bus: The host ASIC continues to drive CMDV HIGH and to apply Search command CMD[1:0] = “10”. CMD[5:2]
must now be driven by the index of the comparand register pair for storing the two 72-bit word presented on the DQ bus
during cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address
of the matching entry and hit flag (see page 27 for a description of SSR[0:7]). CMD[10:9] are don’t cares for this cycle.
— DQ Bus: The DQ[71:0] continues to carry the 72-bit data to be compared.
Note. For 72-bit searches, the host ASIC must supply the same 72-bit data on DQ[71:0] during both cycles A and B. Also, the
even and odd pairs of GMRs selected for the comparison must be programmed with the same value.
CFG are all zeroes for Non-Enhanced Mode,
NES = 00 (binary) in each block for Enhanced Mode.
HLAT = 010 (binary), TLSZ = 01 (binary), LRAM = 1 (binary), LDEV = 1 (binary).
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
Search2
Search4
W
X
Y
Z
10
10
10
10
A B A B A B A B
Addr
z
1
1
0
0
0
0
cycle
CLK2X
CMDV
CMD[1:0]
DQ
CE_L
OE_L
(Miss on
CMD[10:2]
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
PHS_L
SADR[M:0]
SSF
SSV
Search1
Search2
Search3
Search1
Search3
0
(Local
winner but
not global
winner)
|(LHI[6:0])
LHO[1:0]
this device)
(Miss on
this device)
0
z
0
0z
0
ALE_L
WE_L
1z
1
0
z
1 0
Search4
(Global
winner)
Figure 6-12. Timing Diagram for 72-bit Search Device Number 7 (Last Device)
Z
M = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128
0
z
1 0
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