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CYNSE10512 Datasheet(PDF) 53 Page - Cypress Semiconductor

Part # CYNSE10512
Description  Ayama??10000 Network Search Engine
Download  153 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYNSE10512 Datasheet(HTML) 53 Page - Cypress Semiconductor

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CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 53 of 153
Burst Read operation sequence:
• Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[2] = 1) using CMDV = 1, and the address supplied
on the DQ bus. The host ASIC selects the Ayama 10000 device where ID[4:0] matches the DQ[25:21] lines. If
DQ[25:21] = 11111, the host ASIC selects the Ayama 10000 device with the LDEV bit set.
• Cycle 2: The host ASIC floats DQ[71:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[71:0] in a three-state condition.
• Cycle 4: The selected device starts to drive the DQ[71:0] bus and drives ACK and EOT from Z to LOW.
• Cycle 5: The selected device drives the Read data from the address location on the DQ[71:0] bus and drives the ACK signal
HIGH.
Cycles 4 and 5 repeat for each additional access until all the accesses specified in the BLEN field of RBURREG are complete.
On the last data transfer, the Ayama 10000 drives the EOT signal HIGH.
Cycle (4 + 2n): The selected device drives the DQ[71:0] to a three-state condition, and drives ACK and EOT signals LOW.
At the termination of cycle (4 + 2n), the selected device floats ACK and EOT to a three-state condition. The burst Read operation
is complete and the next operation can begin.
6.3.3
Read Parity
Data output of the Read Parity command should be ignored. Read Parity is a blocking operation only on the cycles as the normal
Read operation even though the parity status signal (PARERR) is valid TLSZ cycles later. Figure shows an example of the
PARERR update timing diagram with TLSZ set to “10” (two additional cycles of latency) to a total of eight cycles (six Read cycles
plus two TLSZ cycles).
6.4
Write Command
The Write command can be issued to write to the data array, mask array, NSE-associated SRAMs or internal registers. The Write
can be a single or burst Write (Table 6-3). Burst Write can only be issued for accesses to the data or mask array locations. SRAM
Write operation is covered in Section 6.7.4 to Section 6.7.6. The Write command is also used to issue the Parallel Write command.
Note that when Parity feature is enabled masks will be ignored and all bits will be written as presented in the DQ bus.
CMDV
CMD[1:0]
ACK
EOT
DQ
0
0
Data1
cycle
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
cycle
11
cycle
12
Data0
Data2
0
Data3
0
PHS_L
CMD[10:2]
Address
A B
Read
CLK2X
Figure 6-2. Burst Read of the Data and Mask Arrays (BLEN = 4)
[+] Feedback
[+] Feedback


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