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CYNSE10512 Datasheet(PDF) 45 Page - Cypress Semiconductor

Part # CYNSE10512
Description  Ayama??10000 Network Search Engine
Download  153 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYNSE10512 Datasheet(HTML) 45 Page - Cypress Semiconductor

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CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
Document #: 38-02069 Rev. *F
Page 45 of 153
5.9.2
Addressing the Internal Registers
The following table (Table 5-27) details the parameters expected (in DQ bus) to access the internal registers of the NSE.
Figure 5-31. Internal Register Address Space Encoding
5.10
Depth Cascading
The NSE application can depth-cascade the devices to various table sizes of different widths (72-bit, 144-bit, 288-bit or 576-bit).
The devices perform all the necessary arbitration to decide which device will drive the SRAM bus. Some operations and features
are not cascadable, which means that the operation or feature is on a device-by-device basis and the results are not propagated
to the next device. Table 5-28 lists those operations and features. The following subsections covers the interconnects when the
devices in a cascade operates in the Non-Enhanced mode or Enhanced Mode with MSE set to 0 (MultiSearch disabled). For
device interconnects when operating in Enhanced mode with MultiSearch enabled, please refer to Figure 6-14.
5.10.1
Depth Cascading up to Eight Devices in One Block
Figure 5-32 shows the interconnection of up to eight devices in a cascade to form 2M × 72, 1M × 144, 512K × 288, or 256K x
576 tables. Each NSE asserts the LHO[1] and LHO[0] signals to inform downstream devices of its result. LHI[6:0] signals for a
device are connected to LHO signals of the upstream devices. The host ASIC must program the TLSZ to 01 (binary) for each of
up to eight devices in a block. Only a single device drives the SRAM bus in any single cycle.
Note:
13. Software solutions are possible for these cases. Please refer to specific application notes.
Table 5-27. Internal Register Address Space Encoding
Field
Range
(decimal)
Description
REGSEL
[10:0]
Register Address Selected. This field selects which internal register to address.Table 5-
3 lists the registers that are available.
BLKNUM
[17:11]
Block Number. This field selects the block within the device that will participate in the
operation. It is only used when accessing block specific internal registers (BMR, BPR,
BPAR, BNFA and BPRA0-3). For other internal register accesses, this field must be set to 0.
[18]
Reserved.
RSEL
[20:19]
Register Area Select. This field indicates in what context the access takes place. It must
be set to “11”.
CHIPID
[25:21]
Device ID. This field indicates which NSE device should respond to the READ or WRITE
operation. CHIPID value “11111” indicates a broadcast operation.
[28:26]
Reserved.
INDIRECT
[29]
Indirect Addressing Enable. This bit must be cleared to 0.
[71:30]
Reserved.
Table 5-28. Cascadability of Operations and Features
Operations / # of Devices
Non-Enhanced
Enhanced Mode
with MSE = 0
Enhanced Mode
with MSE = 1
1
2-8
9-31
1
2-8
9-31
1
2-8
9-31
MultiSearch Command
No
No
No
No
No
No
Yes
Yes
No
Learn Command
Yes
Yes
No
Yes
Yes
No[13]
Yes
No[13]
No[13]
Soft Priority
No
No
No
Yes
No[13]
No[13]
Yes
No[13]
No[13]
FULL
Yes
Yes
No
Yes
Yes
No
Yes
No
No
MULTI_HIT
Yes
No
No
Yes
No
No
Yes
No
No
7
15
23
0
39
47
55
31
63
71
REGSEL
CHIPID
BLKNUM
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