CYK128K16MCCB
Document #: 38-05584 Rev. *C
Page 4 of 9
AC Test Loads and Waveforms
Parameters
3.0V VCC
Unit
R1
22000
Ω
R2
22000
Ω
RTH
11000
Ω
VTH
1.50
V
Switching Characteristics Over the Operating Range [10]
Parameter
Description
55 ns[14]
70 ns
Unit
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
55[14]
70
ns
tAA
Address to Data Valid
55
70
ns
tOHA
Data Hold from Address Change
5
10
ns
tACE
CE LOW to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
tLZOE
OE LOW to LOW Z[11, 13]
55
ns
tHZOE
OE HIGH to High Z[11, 13]
25
25
ns
tLZCE
CE LOW to Low Z[11, 13]
25
ns
tHZCE
CE HIGH to High Z[11, 13]
25
25
ns
tDBE
BLE/BHE LOW to Data Valid
55
70
ns
tLZBE
BLE/BHE LOW to Low Z[11, 13]
55
ns
tHZBE
BLE/BHE HIGH to HIGH Z[11, 13]
10
25
ns
tSK
[14]
Address Skew
0
10
ns
Write Cycle[12]
tWC
Write Cycle Time
55
70
ns
tSCE
CE LOW to Write End
45
60
ns
tAW
Address Set-Up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
40
45
ns
Notes:
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels
of 0V to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
12. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write
13. High-Z and Low-Z parameters are characterized and are not 100% tested.
14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are
stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.
VCC
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT
VTH
Equivalent to:
THÉVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
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