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CYD18S36V-100BBC Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CYD18S36V-100BBC
Description  FLEx36??3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYD18S36V-100BBC Datasheet(HTML) 4 Page - Cypress Semiconductor

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CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Document Number: 38-06076 Rev. *F
Page 4 of 28
Pin Definitions
Left Port
Right Port
Description
A0L–A18L
A0R–A18R
Address Inputs.
BE0L–BE3L
BE0R–BE3R
Byte Enable Inputs. Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
BUSYL
[2,5]
BUSYR
[2,5]
Port Busy Output. When the collision is detected, a BUSY is asserted.
CL
CR
Input Clock Signal.
CE0L
[11]
CE0R
[11]
Active Low Chip Enable Input.
CE1L
[10]
CE1R
[10]
Active High Chip Enable Input.
DQ0L–DQ35L
DQ0R–DQ35R
Data Bus Input/Output.
OEL
OER
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ
data pins during Read operations.
INTL
INTR
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The
upper two memory locations can be used for message passing. INTL is asserted LOW
when the right port writes to the mailbox location of the left port, and vice versa. An interrupt
to a port is deasserted HIGH when it reads the contents of its mailbox.
LowSPDL
[2,4]
LowSPDR
[2,4]
Port Low Speed Select Input.
PORTSTD[1:0]L
[2,4] PORTSTD[1:0]
R
[2,4] Port Address/Control/Data IO Standard Select Inputs.
R/WL
R/WR
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual
port memory array.
READYL
[2,5]
READYR
[2,5]
Port Ready Output. This signal is asserted when a port is ready for normal operation.
CNT/MSKL
[10]
CNT/MSKR
[10]
Port Counter/Mask Select Input. Counter control input.
ADSL
[11]
ADSR
[11]
Port Counter Address Load Strobe Input. Counter control input.
CNTENL
[11]
CNTENR
[11]
Port Counter Enable Input. Counter control input.
CNTRSTL
[10]
CNTRSTR
[10]
Port Counter Reset Input. Counter control input.
CNTINTL
[12]
CNTINTR
[12]
Port Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of
the counter is incremented to all “1s”.
WRPL
[2,3]
WRPR
[2,3]
Port Counter Wrap Input. The burst counter wrap control input.
RETL
[2,3]
RETR
[2,3]
Port Counter Retransmit Input. Counter control input.
FTSELL
[2,3]
FTSELR
[2,3]
Flow-Through Select. Use this pin to select Flow-Through mode. When is de-asserted,
the device is in pipelined mode.
VREFL
[2,4]
VREFR
[2,4]
Port External High-Speed IO Reference Input.
VDDIOL
VDDIOR
Port IO Power Supply.
REVL
[2, 3, 4]
REVR
[2, 3, 4]
Reserved pins for future features.
MRST
Master Reset Input. MRST is an asynchronous input signal and affects both ports. A
maser reset operation is required at power up.
TRST[2,5]
JTAG Reset Input.
TMS
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
TDI
JTAG Test Data Input. Data on the TDI input is shifted serially into selected registers.
TCK
JTAG Test Clock Input.
TDO
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is
normally three-stated except when captured data is shifted out of the JTAG TAP.
VSS
Ground Inputs.
VCORE
[13]
Core Power Supply.
VTTL
LVTTL Power Supply for JTAG IOs
[+] Feedback


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