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CY62147CV18 Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CY62147CV18
Description  256K x 16 Static RAM
Download  11 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY62147CV18 Datasheet(HTML) 1 Page - Cypress Semiconductor

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256K x 16 Static RAM
CY62147CV18 MoBL2™
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05011 Rev. *C
Revised August 28, 2002
Features
• High speed
— 55 ns and 70 ns availability
• Low voltage range:
— 1.65V
−1.95V
• Pin-compatible w/ CY62147BV18
• Ultra-low active power
— Typical Active Current: 0.5 mA @ f = 1 MHz
— Typical Active Current: 2 mA @ f = fmax (70 ns speed)
• Low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The CY62147CV18 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE HIGH or both BLE and BHE are HIGH). The
input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when: deselected (CE HIGH), outputs
are disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the Truth Table at the back of this data sheet for a complete
description of read and write modes.
The CY62147CV18 is available in a 48-ball FBGA package.
Logic Block Diagram
256K x 16
RAM Array
I/O0–I/O7
COLUMN DECODER
2048 X 2048
DATA IN DRIVERS
OE
I/O8–I/O15
CE
WE
BLE
BHE
A7
A6
A3
A0
A2
A1
A5
A4
A8
Power-down
Circuit
BHE
BLE
CE
A9
A10


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