1 Mb (64K x 16) Static RAM
PRELIMINARY
CY62127DV18
MoBL2®
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-05226 Rev. *A
Revised May 5, 2005
Features
• Very high speed: 55 ns
• Voltage range: 1.65V to 2.2V
• Ultra-low active power
— Typical active current: 0.5 mA @ f = 1 MHz
— Typical active current: 3.75 mA @ f = fMAX
• Ultra-low standby power
• Easy memory expansion with CE</> and OE</> fea-
tures
• Automatic power-down when deselected
• Packages offered in a 48-ball FBGA and a 44-lead TSOP
Type II
Functional Description[1]
The CY62127DV18 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life
™ (MoBL®) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption by 99% when addresses are not toggling.
The device can be put into standby mode reducing power con-
sumption by more than 99% when deselected Chip Enable
(CE) HIGH or both BHE and BLE are HIGH. The input/output
pins (I/O0 through I/O15) are placed in a high-impedance state
when: deselected Chip Enable (CE) HIGH, outputs are dis-
abled (OE HIGH), both Byte High Enable and Byte Low Enable
are disabled (BHE, BLE HIGH) or during a write operation
(Chip Enable (CE) LOW and Write Enable (WE) LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) LOW and Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through
I/Os pins (A0 through A15). If Byte High Enable (BHE) is LOW,
then data from I/O pins (I/O8 through I/O15) is written into the
location specified on the ad
Reading from the device is accomplished by taking Chip En-
able (CE) LOW and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then O7. If Byte High Enable (BHE) is LOW, then data from
memory will appear on I/O8 to I/O15. See the truth table at the
back of this data sheet for a complete description of re
Note:
1.
For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
64K x 16
RAM Array
I/O0–I/O7
COLUMN DECODER
2048 X 512
DATA IN DRIVERS
OE
I/O8–I/O15
CE
WE
BLE
BHE
A7
A6
A3
A0
A2
A1
A5
A4
A8
Power -Down
Circuit
BHE
BLE
CE
A9
A10
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