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CY29940-1
Document #: 38-07487 Rev. **
Page 4 of 7
Notes:
7.
Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
8.
Across temperature and voltage ranges, includes output skew.
9.
For a specific temperature and voltage, includes output skew.
10. Parameters tested @ 150 MHz.
AC Electrical Specifications (VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%)
[7]
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Fmax
Input Frequency
LVCMOS Input
200
MHz
LVPECL Input
180
TPD
PECL_CLK to Q Delay[4,5,10]
</ =150 MHz
VDD = 3.3V
2.0
4.0
ns
VDD = 2.5V
2.6
5.2
LVCMOS to Q Delay[4,5,10]
</ =150 MHz
VDD = 3.3V
1.8
3.4
VDD = 2.5V
2.3
4.0
FoutDC
Output Duty Cycle[4,5,6]
FCLK < 134 MHz
45
55
%
FCLK > 134 MHz
40
60
Tskew
Output-to-Output Skew[4,5]
150
ps
Tskew(pp)
Part-to-Part Skew[8]
PECL, VDDC = 3.3V
1.4
ns
PECL, VDDC = 2.5V
2.2
Tskew(pp)
Part-to-Part Skew[8]
TCLK, VDDC = 3.3V
1.2
ns
TCLK, VDDC = 2.5V
1.7
Tskew(pp)
Part to Part Skew[9]
PECL_CLK
850
ps
TCLK
750
tR/tF
Output Clocks Rise/Fall Time[4,5]
0.7V to 2.0V,
VDDC = 3.3V
0.3
1.1
ns
0.5V to 1.8V,
VDDC = 2.5V
0.3
1.3
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
VTT
Zo = 50 ohm
VTT
RT = 50 ohm
RT = 50 ohm
CY29940-1 DUT
Figure 1. LVCMOS_CLK CY29940-1 Test Reference for VCC = 3.3V and VCC = 2.5V
Differential
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
VTT
RT = 50 ohm
CY29940-1 DUT
Zo = 50 ohm
RT = 50 ohm
VTT
Figure 2. PECL_CLK CY29940-1 Test Reference for VCC = 3.3V and VCC = 2.5V
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