2.5V or 3.3V, 200-MHz, 9-Output Clock Driver
CY29350
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07474 Rev. *A
Revised July 26, 2004
Features
• Output frequency range: 25 MHz to 200 MHz
• Input frequency range: 6.25 MHz to 31.25 MHz
• 2.5V or 3.3V operation
• Split 2.5V/3.3V outputs
• ±2.5% max Output duty cycle variation
• Nine Clock outputs: Drive up to 18 clock lines
• Two reference clock inputs: Xtal or LVCMOS
• 150-ps max output-output skew
• Phase-locked loop (PLL) bypass mode
• Spread Aware™
• Output enable/disable
• Pin-compatible with MPC9350
• Industrial temperature range: –40°C to +85°C
• 32-pin 1.0mm TQFP package
Functional Description
The CY29350 is a low-voltage high-performance 200-MHz
PLL-based clock driver designed for high speed clock distri-
bution applications.
The CY29350 features Xtal and LVCMOS reference clock
inputs and provides nine outputs partitioned in four banks of 1,
1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4
while the other banks divide by 4 or 8 per SEL(A:D) settings,
see . These dividers allow output to input ratios of 16:1, 8:1,
4:1, and 2:1. Each LVCMOS compatible output can drive 50
Ω
series or parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:18.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 25 MHz to 200 MHz. The internal
VCO is running at multiples of the input reference clock set by
the feedback divider, see Table 1.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
Pin Configuration
OSC
Phase
Detector
VCO
200 -
500MHz
LPF
÷16 / ÷32
÷2 / ÷4
÷4 / ÷8
÷4 / ÷8
÷4 / ÷8
QA
QB
QC0
QC1
QD0
QD1
QD2
QD3
QD4
SELA
PLL_EN
TCLK
REF_SEL
XIN
XOUT
FB_SEL
SELB
SELC
OE#
SELD
CY29350
QC0
VDDQC
QC1
VS S
QD0
VDDQD
QD1
VS S
AVD D
FB_SEL
SELA
SELB
SELC
SELD
AVSS
XO UT
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
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