CY28551LFXC datasheet(6/30 Pages) CYPRESS

Part #	CY28551LFXC

Description	Universal Clock Generator for Intel, VIA, and SIS짰

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY28551

Document #: 001-05675 Rev. *C

Page 6 of 30

Control Registers

Byte 0: Control Register 0

Bit

@Pup

Type

Name

Description

7

1

R/W

PCIEX[T/C]7

PCIEX[T/C]7 Output Enable

0 = Disable (Tri-state), 1 = Enable

6

1

R/W

PCIEX[T/C]6

PCIEX[T/C]6 Output Enable

0 = Disable (Tri-state), 1 = Enable

5

1

R/W

PCIEX[T/C]5

PCIEX[T/C]5 Output Enable

0 = Disable (Tri-state), 1 = Enable

4

1

R/W

PCIEX[T/C]4

PCIEX[T/C]4 Output Enable

0 = Disable (Tri-state), 1 = Enable

3

1

R/W

PCIEX[T/C]3

PCIEX[T/C]3 Output Enable

0 = Disable (Tri-state), 1 = Enable

2

1

R/W

PCIEX[T/C]2

PCIEX[T/C]2 Output Enable

0 = Disable (Tri-state), 1 = Enable

1

R/W

PCIEX[T/C]1

PCIEX[T/C]1 Output Enable

0 = Disable (Tri-state), 1 = Enable

0

1

R/W

SATA/PCIEX[T/C]0

SATA/PCIEX[T/C]0 Output Enable

0 = Disable (Tri-state), 1 = Enable

Byte 1: Control Register 1

Bit

@Pup

Type

Name

Description

7

1

R/W

SATA/DOT96]

SATA/DOT96Output Enable

0 = Disable (Tri-state), 1 = Enable

6

1

R/W

24_48M

24_48M Output Enable

0 = Disable, 1 = Enable

5

1

R/W

48M

48M Output Enable

0 = Disable, 1 = Enable

4

1

R/W

REF2

REF2 Output Enable

0 = Disable, 1 = Enable

3

1

R/W

REF1

REF1 Output Enable

0 = Disable, 1 = Enable

2

1

R/W

REF0

REF0 Output Enable

0 = Disable, 1 = Enable

1

R/W

CPU[T/C]1

CPU[T/C]1 Output Enable

0 = Disable (Tri-state), 1 = Enable

0

1

R/W

CPU[T/C]0

CPU[T/C]0 Output Enable

0 = Disable (Tri-state), 1 = Enable

Byte 2: Control Register 2

Bit

@Pup

Type

Name

Description

7

1

R/W

Reserved

6

1

R/W

PCI6_F

PCI6_F Output Enable

0 = Disable, 1 = Enable

5

1

R/W

PCI5

PCI5 Output Enable

0 = Disable, 1 = Enable

4

1

R/W

PCI4

PCI4 Output Enable

0 = Disable, 1 = Enable

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CY28551LFXC Datasheet(PDF) 6 Page - Cypress Semiconductor

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