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CY28517ZXC Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY28517ZXC
Description  PCI Express Clock Generator
Download  12 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY28517ZXC Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY28517
Document #: 001-42225 Rev. *A
Page 7 of 12
Figure 2. Crystal Loading Example
Use the following formulas to calculate the trim capacitor values
for Ce1 and Ce2.
CL ................................................... Crystal load capacitance
CLe ......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce ..................................................... External trim capacitors
Cs ..............................................Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
Output Enable
The Output Enable (OE_100_25) signal is active HIGH input
used for clean stopping and starting the selected 100M and 25M
outputs. To recognize as a valid assertion or deassertion, the
signal is a debounced signal in that its state must remain
unchanged during two consecutive rising edges of 25 MHz.
The assertion and deassertion of this signal is absolutely
asynchronous.
Output Enable Deassertion
Upon deasserting the Output Enable pin (OE_100_25) all
100M/25M outputs are stopped after their next transition. The
final state of all stopped 100M/25M signals is LOW.
Output Enable Assertion
All 100 MHz/25 MHz outputs that were stopped resumes normal
operation in a glitch free manner. The maximum latency from the
assertion to active outputs is between 2–6 clock periods of
100 MHz/25 MHz with all 100M/25M outputs resuming simulta-
neously.
XTAL
Ce 2
Ce 1
Cs 1
Cs 2
X1
X2
Ci1
Ci2
Clo c k Ch ip
Tr a c e
2. 8pF
Tr im
33pF
Pin
3 t o 6p
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
(
)
1
=
CLe
Table 6. Output Enable Table
Output Enable
27M
48M
25M[A:B] 100MT/C[A:D]
0
On
On
Low
Hi-Z
1On
On
On
On
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
VDD
Supply Voltage
–0.5
4.6
V
VIN
Input Voltage
Relative to VSS
–0.5
VDD + 0.5
VDC
TS
Temperature, Storage
Non-functional
–65
150
°C
TA
Temperature, Operating Ambient
Functional
5
65
°C
TJ
Temperature, Junction
Functional
150
°C
TSOL
Pb free Soldering Process Temperature
260
°C
ESDHBM
ESD Protection (Human Body Model)
MIL-STD-883, Method 3015
2000
V
UL-94
Flammability Rating
At 1/8 in.
V–0
MSL
Moisture Sensitivity Level
1
Multiple Supplies: The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is
NOT required.
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