PRELIMINARY
CY28341-3
Document #: 38-07580 Rev. **
Page 7 of 19
4
1
31,32
DDRT/C4
1 = output enabled (running). 0 = output disabled asynchronously in a low state.
3
1
35,36
DDRT/C3
1 = output enabled (running). 0 = output disabled asynchronously in a low state.
2
1
37,38
DDRT/C2
1 = output enabled (running). 0 = output disabled asynchronously in a low state.
1
1
41,42
DDRT/C1
1 = output enabled (running). 0 = output disabled asynchronously in a low state.
0
1
43,44
DDRT/C0
1 = output enabled (running). 0 = output disabled asynchronously in a low state.
Byte 6: Watchdog Register
Bit
@Pup
Pin#
Name
Description
7
0
26
SRESET#
1 = Pin 26 is the input pin as PD# signal. 0 = Pin 26 is the output pin as
SRESET# signal.
6
0
Frequency Revert
This bit allows setting the Revert Frequency once the system is rebooted
due to Watchdog time out only. 0 = select frequency of existing H/W setting,
1 = select frequency of the second to last S/W table setting. (the software
setting prior to the one that caused a system reboot).
5
0
WDTEST
For IMI Test - WD-Test, ALWAYS program to '0'
40
WD Alarm
This bit is set to “1” when the Watchdog times out. It is reset to “0” when the
system clears the WD time stamps (WD3:0).
30
WD3
This bit allows the selection of the time stamp for the Watchdog timer. See
Table 7
20
WD2
This bit allows the selection of the time stamp for the Watchdog timer. See
Table 7
10
WD1
This bit allows the selection of the time stamp for the Watchdog timer. See
Table 7
00
WD0
This bit allows the selection of the time stamp for the Watchdog timer. See
Table 7
Table 7. Watchdog Time Stamp
WD3
WD2
WD1
WD0
FUNCTION
00
0
0
Off
0
0
0
1
1 second
0
0
1
0
2 seconds
0
0
1
1
3 seconds
0
1
0
0
4 seconds
0
1
0
1
5 seconds
0
1
1
0
6 seconds
0
1
1
1
7 seconds
1
0
0
0
8 seconds
1
0
0
1
9 seconds
1
0
1
0
10 seconds
1
0
1
1
11 seconds
1
1
0
0
12 seconds
1
1
0
1
13 seconds
1
1
1
0
14 seconds
1
1
1
1
15 seconds
Byte 5: SDR/DDR Clock Register (continued)
Bit
@Pup
Pin#
Name
Description
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